Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 71
Table42: Keyboard Control/Status Register CSR
To signal service requests the keyboard controller interrupt signal is
connected to the VICs LIRQ1 input. The VIC has to be programmed to
level-sensitive and has to supply the vector. The receiver interrupt can be
enabled by the LIRQ1 of the VIC. If the transmitter interrupt enable (TIE)
in the control register is set and the interrupts are enabled by the VIC,
receiver and transmitter interrupts are serviced by the CPU.
- -- - - - RBF TBE
D7 D0
Name: Control/Status Register
Shortname: CSR
Address: $FEC6.0001
TBE - Transmit Buffer Empty
0 The transmit buffer is full and data transmission is in
progress. Writing data to the data register with TBE
clear will destroy the data byte which is currently
transmitted.
1 The transmit buffer is empty. Data can be written into
the data register. The write access to the data registers
clears the TBE.
RBF - Receive Buffer Full
0 The receive buffer is empty. No valid data is available in
the data register.
1 The receive buffer is full. The received data is available
in the data register. Reading the data register clears the
RBF bit.
- -- TIE - - - -
D7 D0
TIE - Transmit Interrupt Enable
0 The transmit interrupt is disabled.
1 The transmitter interrupt is enabled. The keyboard
controller requests an interrupt if the transmit register is
empty. The TIE must be cleared within the interrupt
service routine if the data register is not loaded with a
new data byte. Otherwise the interrupt output of the
keyboard controller will stay active.
Readable bits
Writable bits