Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 69
3.8 Watchdog Timer
The watchdog timer installed on the EUROCOM-17-5xx monitors the
activity of the microprocessor. If the microprocessor does not write
location $FEC5.0000 within the time-out period of 100ms (min.70ms;
max. 140ms) or 1.6s (±30%), a reset pulse is generated. After reset, the
watchdog timer is disabled. The normal time-out period of 100ms
becomes effective after the first write access to address $FEC5.0000.
If the watchdog timer generates a reset pulse, the left decimal point of the
hex display located at the front panel is illuminated to indicate a watchdog
reset. This watchdog indicator is cleared by power-up reset, the reset
switch, a VMEbus SYSRESET, a VIC remote reset, or by a write access
to address $FEC5.0000.
The state of the watchdog indicator can be read by software using port A
of the system CIO ($FEC3.0002). If the left decimal point of the hex
display is illuminated, PA7 of the system CIO is read as '0'. As a result of
this, software can distinguish between a watchdog reset and a reset
generated by the other sources.
If the watchdog timer function is enabled at the first access to
$FEC5.0000, $FEC5.0000 must be accessed within the time-out period of
100ms!
Table40: Address Assignment of Watchdog Registers
Address Description Access
Direction
$FEC3.0002 Port A Data Register System CIO read PA7
$FEC5.0000 Watchdog trigger write
i