Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 63
• In interlaced mode bit 2 of the TRMIB register can be used to swap the
contents of the two frames.
• For interlaced operation REG4 of the LM1882 must be even.
• For interlaced operation with an odd number of lines (CCIR, EIA), the
first and the last displayed line should be set to black because they are
only displayed half.
• Interlaced mode can only be used when the SPLIT bit in the GRMODE
register is clear.
• /PSYNC and /PHSYNC outputs of the Bt445 should never be enabled
simultaneously because they are tied together.
3.4.8 Screen
Resolutions
Table34: Screen Resolutions
3.4.9 Digital Video
Output
Digital video output is enabled when J1202 is set and RN1201 is removed.
J1201 selects whether inverted or non-inverted clock is sent to the display.
This allows to satisfy the data setup- and hold times of a particular display
type.
When using digital output it is essential to connect the display via a short
piece of cable with minimum crosstalk and even propagation delay. Also
the cable should be terminated at the display side. For distances up to 1m,
a flat cable with alternating ground and signal wires should be sufficient.
The best solution, of course, are single shielded wires.
On the VGA connector the most significant bits of red, green, and blue
and the second most significant bit of blue are available. The translation of
the bits in the video memory to these bits can be programmed via the color
palette of the Bt445.
Resolution
hor. x ver.
Horizontal
Frequency
Vertical
Frequency
Dotclock Video
Standard
1152 x 872 69.0kHz 75Hz 100MHz -
1152 x 900 62.0 kHz 66Hz 93MHz SUN like
1024 x 768 56.0 kHz 70 Hz 80 MHz SVGA like
1024 x 768 48.0kHz 60Hz 65MHz SVGA like
800 x 600 48.0 kHz 72 Hz 50 MHz SVGA like
800 x 600 38.0kHz 60Hz 40MHz SVGA like
640 x 480 31.5 kHz 60 Hz 25 MHz VGA like