Hardware manual

3 Programmers Reference EUROCOM-17-5xx

62 Hardware Manual

Figure8: Pixel Model

For 1/2/4 bit per pixel operation, the most significant part of each byte

represents the leftmost pixel and the least significant part represents the

rightmost pixel on the screen.

3.4.6 Overlay

Memory

The overlay memory has the same structure as the video memory. It starts

at $0FE0.0000 and uses only the least significant nibble of each byte.

Overlay memory cannot be written with byte operations because the write

enables of two adjacent pixels are tied together.

Overlay is only available when the video memory operates in 8-bit per

pixel mode.

3.4.7 Video

Parameter

Restrictions

The EUROCOM-17-5xx graphic interface is rather freely programmable.

However, some restrictions must be observed:

• Dotclock for analog output from 10MHz to 120MHz

• Dotclock for digital output from 10MHz to 55MHz

• Maximum SCLK (shift clock for serial port of VRAM) must be either

30MHz or dotclock divided by two (whatever is less)

• Maximum VIDCLK (clock for sync generator) must be either 30MHz or

dotclock divided by two (whatever is less)

• PLL clock from 75MHz to 150MHz

• PLL reference clock is 25.175MHz

• TRINC of the address register must be programmed to 512 for packed

line format (i.e. if the SPLIT bit in the GRMODE register is set)

• TRINC of the address register must be programmed to 2048 for

interlaced operation (this results in a pitch of 1024 bytes between two

lines).

Pixel n+1 Pixel n+2 Pixel n+3Pixel n

D31

longword boundary

Address $x+1 Address $x+2 Address $x+3Address $x0