Hardware manual

3 Programmers Reference EUROCOM-17-5xx
60 Hardware Manual
Table33: Register of Address and Sync Generator
3.4.2 Accessing the
Internal
Register of the
Bt445
The Bt445 uses an indirect addressing scheme. To access a register, its
indirect address must be written to the BT_ADR register at $FEC4.0000.
Then the register can be accessed with a byte write or read operation to the
appropriate direct address (see Table32: ‘Register of Bt445’). After the
access, the Bt445 increments the address register by one so that the
following register can be accessed without writing the address register.
Some registers use modulo 3 addressing. In this case incrementing will
occur only every third access.
Address Name Description
$FEC4.8000 TRLSB Transfer Address Least Significant Byte
$FEC4.8001 TRMIB Transfer Address Middle Byte
$FEC4.8002 TRMSB Transfer Address Most Significant Byte
$FEC4.8003 Reserved
$FEC4.8004 TRINC Address Increment (pitch) in 128 byte steps:
$01 = 128 bytes
$02 = 256 bytes
$03 = 384 bytes
. .
$0F = 1920 bytes
$00 = 2048 bytes
$FEC4.8005 GRMODE Bit No. Name Description
0 SPLIT 0 = sync. transfer,
1 = split transfer
1 DISOVERL 0 = 8 bit per pixel + 4 bit overlay
1 = 1/2/4/8 bit per pixel
2 PIXDEL 0 = don't delay digital pixel
data,
1 = delay digital pixel data
3 INTERL 0 = noninterlaced,
1 = interlaced
4 ENTRA 0 = disable address transfer
cycles,
1 = enable address transfer
cycles
5 COMPSYN 1 = composite sync.,
0 = separate sync.
$FEC4.8006 ADR1882 LM1882 Address Register
$FEC4.8007 DAT1882 LM1882 Data Register