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elektronik mainz

EUROCOM-27

Dual 68060 CPU Board with Graphics

Hardware Manual

Revision 1 A

Summary of content (144 pages)

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elektronik mainz EUROCOM-27 Dual 68060 CPU Board with Graphics Hardware Manual Revision 1 A
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Revision History Rev. 1A EUROCOM-27 Changes Changes Date First Edition valid for EUROCOM-27 Hardware Revision 1.A 31.01.95, T.K. WARNING ! This equipment generates and can radiate radio frequencies. If not installed in accordance with the instruction manual, it may cause interference to radio communications.
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EUROCOM-27 Table of Contents Table of Contents Page Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents (Continued) EUROCOM-27 Page 1.3.15 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3.16 Status Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3.17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3.18 VMEbus Interface . . . . . . . . . . . . . . . . .
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EUROCOM-27 Table of Contents (Continued) Page 2.1.5 Pure 8-bit SCSI Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1.6 Pure 16-bit SCSI Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.1.7 Mixed 8/16 bit SCSI Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 Default Board Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents (Continued) EUROCOM-27 Page 3.3 3.4 VMEbus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.1 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.2 VMEbus Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.2.1 Longword Access to Wordwide Slaves . . . . . . . . . .
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EUROCOM-27 Table of Contents (Continued) Page 3.13 Battery-Backed Parameter RAM and Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.13.1 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.13.2 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.14 VIC Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables EUROCOM-27 List of Tables Page Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: CAS2 Operations on the Various Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Usable Bandwidth of the RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 15-Pin VGA Connector (MONITOR PORT X1201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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EUROCOM-27 List of Tables (Continued) Page Table 35: Table 36: Table 37: Table 38: Table 39: Address Assignment of the CIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCIO, UCIO Interrupt Level Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Level Assignment for SCIO, UCIO and FR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time Constant Values for MPC . . . . . . . . . . . . . . . . . . . . . . .
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List of Figures EUROCOM-27 List of Figures Page Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: VIII Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Overlay Pixel Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Graphic Interface Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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EUROCOM-27 Scope of Delivery / Options Scope of Delivery Description: Order No.: EUROCOM-27 Single 68060, 50 MHz, VME-32 SCSI, Ethernet, Graphics, 32 MB V-E27.-A139 EUROCOM-27 Single 68060, 50 MHz, VME-32 SCSI, Ethernet, Graphics, 8 MB V-E27.-A113 EUROCOM-27 Double 68060, 50 MHz, VME-32 SCSI, Ethernet, Graphics, 32 MB V-E27.-A239 Options Description: Order No.: VIC-64 instead of VIC-32 i V-E17.
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Related Products EUROCOM-27 Related Products Description: Order No.: Documentation: Hardware Manual EUROCOM-27 V-E27.-A990 Service Manual EUROCOM-27 including: V-E27.-A991 Software Manual RMon (W-FIRM-A209) Hardware Manual CONV-300 (V-CONV-A993) LEB Specification (V-LEB.
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EUROCOM-27 Conventions Conventions If not otherwise specified, addresses are written in hexadecimal notation and identified by a leading dollar sign ("$"). Signal names preceded by a slash ("/"), indicate that this signal is either active low or that this signal becomes active with the trailing edge.
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Conventions (Continued) EUROCOM-27 MBLT MPC PCB PLL RAM RBF RMC RTC RTS SBR SCSI SCR SILC SRAM SMR TBE TTL VIC VRAM VTG UAT XII Multiplexed Block Transfer Multi-Protocol Controller Printed Circuit Board Phase Locked Loop Random Access Memory Receive Buffer Full Read-Modify-Write Cycle Real-time Clock Request to Send Slave Base Address Register Small Computer Systems Interface System Control Register Serial Interface Level Converter Static RAM Slave Mask Register Transmit Buffer Empty Transistor Transist
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EUROCOM-27 How to Use this Manual How to Use this Manual Document Structure This manual is divided into the following chapters: Chapter 1 Specification contains a list of distinguishing features, a block diagram with a general description, a description of the main building blocks and the board parameters. Chapter 2 Installation describes the requirements and the step-by-step installation.
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How to Use this Manual (Continued) EUROCOM-27 Other Conventions: i ! Indicates information that requires close attention. Indicates critical information that is essential to read. Indicates information that is imperative to read. Skipping this material, possibly causes damage to the system.
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1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Distinguishing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Technical Details . . . . . . . . . . . . . . . . . . . . . . . . . .
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PRELIMINARY 1.5.1 VMEbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.2 LEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.3 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5.4 SCSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2.3.8.2 Hardware Configuration (S902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.8.3 System Controller Switch (S3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3 Programmers Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 DRAM .
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PRELIMINARY 3.6 CIO Counter / Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.7 Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.7.1 Multi-Protocol Controller (MPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.8 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.21.1 Deadlock Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.21.2 TAS Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 A.1Mnemonics Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 A.1.1 Addressing Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PRELIMINARY 6
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Table 1: CAS2 Operations on the Various Busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2: Usable Bandwidth of the RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3: 15-Pin VGA Connector (MONITOR PORT X1201) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4: 6-Pin Miniature Circular (mini-DIN) Connector (KEYBOARD X2)19 Table 5: 6-Pin Telephone Jack Connector CHAN.
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Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: 8 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 System Control Register Layout (System CIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 VIC Interrupt Priority Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Local Interrupt Sources .
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Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Overlay Pixel Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Graphic Interface Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Installation Diagram . . . . . . . . . . . . . . .
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10
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A Address Map . . . . . . . . . . . . . . . . . . . . . . . . . 45 Address Modifier Source . . . . . . . . . . . . . . . 51 Address Translation . . . . . . . . . . . . . . . . . . . 48 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 71 B Bandwidth of the RAM . . . . . . . . . . . . . . . . . . 9 basic EPROM . . . . . . . . . . . . . . . . . . . . . . . . 10 baud rate generator . . . . . . . . . . . . . . . . . . . .
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H hardware handshake . . . . . . . . . . . . . . . . . . . 13 I ICF1 decoder . . . . . . . . . . . . . . . . . . . . . . 48, 53 ICF2 decoder . . . . . . . . . . . . . . . . . . . . . . 48, 53 ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 interleaved DRAM . . . . . . . . . . . . . . . . . . . . . 4 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . 17 IOALR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 IOC-2 . . . . . . . . . . . . . . . . . . . . . . . .
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R RAM . . . . . . . . . . . . . . . . . . . . . . . 9, 47, 49, 50 RAM Mirror . . . . . . . . . . . . . . . . . . . . . . . . . 49 RBF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Read-Modify-Write Cycles . . . . . . . . . . . . . . 51 Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . 74 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 76 RMon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 S SBR . . . . . . . . . . . . . . . . . . . . . . . . .
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14
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EUROCOM-17-5xx 1 Specification 1 Specification 1.
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1 Specification EUROCOM-17-5xx •IOC-2 gate array: - 68040 to 68020 bus converter - Dynamic bus sizing for VMEbus and LEB - Translation of BLT into bursts on '040 bus to allow snooping of BLT cycles - Separate arbitration on '040 and '020 bus - I/O bus interface - Support for VMEbus UATs to allow snooping - Interface for a single bytewide EPROM •Parallel I/O or Centronics port •Six 16-bit timer / counter •Four serial ports (RS 232, RS 422, RS 485) •Smart SCSI-2 (NCR 53C720) interface with burst capability
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EUROCOM-17-5xx 1 Specification 1.2 General Description Figure 1: Block Diagram Aux. CPU 68040 40 MHz Memory Module max. 252 MB NCR53C720 SCSI Controller VMEbus 8/16-bit SCSI-2 X101 CPU 68040 40 MHz ‘040 Bus Overlay 512K VRAM 1 MB VRAM I/O Bus Front Panel IOC-2 MUX CIO 8536 Display Video Controller CLUT ‘020 Bus Watchdog Slave Addr. VMEbus Controller VMEbus Buffer/Count./ Decoder 1M x 8 User EPROM Operation Mode 256K x 8 Basic EPROM VIC Res/Stat.
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1 Specification EUROCOM-17-5xx The EUROCOM-17-5xx is a highly integrated high-performance singleboard VMEbus computer with graphics display. It is designed to offer as many features as possible on a single slot VMEbus board. Suitable intelligent or high integrated components are used to achieve this density of computing power. There are two on-board 68040 CPUs, each clocked at 25, 33 or 40 MHz. On-chip caches for program and data (4 KB capacity each) and the onchip floating-point units allow 35 MIPS/ 5.
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EUROCOM-17-5xx 1 Specification One of the main design goals of the EUROCOM-17-5xx is efficient use of the CPU's high speed bus. Thus, the following design rules are established: •Use of intelligent peripheral devices which are able to perform tasks independent from the main CPU (NCR 53C720, CL-CD2401, ILACC). •Independent 68020-like bus for VMEbus, Ethernet or LEB with separate arbitration. •Minimum interference between CPU bus, ‘020 bus and I/O bus. •Decoupling of VMEbus and CPU bus via FIFO for BLT.
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1 Specification EUROCOM-17-5xx The integrated real-time clock allows the operating system to provide date and time for revision control. The clock is powered by an internal lithium battery. 2 (8, 32) KB of battery-backed RAM are used for storage of system dependent parameters. An AT-compatible keyboard input (using a 6-pin PS/2 compatible connector) along with the graphics output provides a PC-type user interface. Status display, reset switch, and two hex-code switches are located on the front panel.
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EUROCOM-17-5xx 1 Specification 1.3 Technical Details The EUROCOM-17-5xx consists of the following main blocks: •CPUs •RAM Module •Basic EPROM •User EPROM •Graphics Interface •Keyboard Interface •Ethernet Interface •SCSI Interface •Serial I/0 •Parallel I/O •CIO Counters / Timers •Parameter RAM and Real-Time Clock •Revision EEPROM •VIC Timer •Watchdog Timer •Status Display •Reset •VMEbus Interface •Interrupt Sources •Local Extension Bus •Software •Connectors 1.3.
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1 Specification EUROCOM-17-5xx CPU1 handles all interrupts generated by the VIC. CPU2 can interrupt CPU1 via the interprocessor communication module switch facility of the VIC. The secondary CPU2 is interrupted by accessing a separate mailbox location by CPU1, by the LEB or by the VIC timer (refer to Table 50: ‘CPU2CON As Seen by Primary CPU’). Additionally, VMEbus interrupts can be handled with some restrictions by the secondary CPU.
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EUROCOM-17-5xx 1.3.2 RAM 1 Specification The DRAM and the video RAM are accessed by the following sources: •CPU1 •CPU2 •SCSI Controller •Ethernet Controller •LEB •VMEbus Burst mode is supported for accesses of: •CPU1 •CPU2 •SCSI Controller •VMEbus BLT The base address of the DRAM seen from the CPUs is fixed to $0000.0000. To avoid programming of the MMU, the DRAM and VRAM are mirrored as non-cacheable RAM. The base address for accessing the RAM from the VMEbus as well as the window size is programmable.
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1 Specification 1.3.3 Basic EPROM EUROCOM-17-5xx After reset, the basic EPROM is mapped to $0000.0000 so the initial stack pointer and reset vector can be read. During initialization, it is mapped to its normal address ($FE80.0000) and the DRAM is located at address $0000.0000. The basic EPROM is accessed with six wait-states (120 ns access time) per byte at 40 MHz. The software in the basic EPROM (RMon) initializes all hardware according to the parameters in the basic EPROM or the NVRAM ($FEC2.0000).
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EUROCOM-17-5xx 1.3.5 Graphics Interface 1 Specification The graphics hardware of the EUROCOM-17-5xx is built in the main by a video sync generator LM1882, a CLUT BT445 and an address generator which is implemented in a MACH445. The PLD provides the appropriate control signals for read/write access, transfer cycles and refresh cycles, too. The programmable video timing generator allows the implementation of different screen resolutions and video standards.
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12 DSF QSF Hardware Manual I/O Bus /RAS MHz 25.175 VIDCLK HSYNC LM1882 Generator CBLANK P(0:63) VCSYNC SCLK 2:1 MUX ‘ 257 Sync VRAM Controller/ Address Generator MACH 445 /CAS TRA(2:19) MUX ‘ 153 4:1 1 MB Video RAM /OE LA(2:19) CPU Bus LD(0:31) GA(0:8) 0.
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EUROCOM-17-5xx 1 Specification 1.3.6 Keyboard Interface The EUROCOM-17-5xx keyboard interface supports PS/2 compatible keyboards. This interface can receive data from and transmit data to the keyboard under interrupt control. The keyboard interface consists of two registers: the data register and the control / status register. 1.3.7 Ethernet Interface The Ethernet interface is based on the Integrated Local Area Communications Controller (ILACC - AM79C900).
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1 Specification 1.3.10 Parallel I/O EUROCOM-17-5xx There is one 8-bit parallel port with handshake signals on the EUROCOM-17-5xx. This parallel port is based on a Zilog Z8536 device (user CIO). The port signals are routed via the VMEbus P2 connector and the ADAP-220/200 to the CONV-300 board. Three 9-pin Sub-D serial plugs, a 25-pin Sub-D parallel connector (Centronics printer interface) and a 26-pin connector for direct access to the CIO pins are installed on the CONV-300.
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EUROCOM-17-5xx 1.3.15 Watchdog Timer 1 Specification The watchdog timer monitors the activity of the microprocessor. If the microprocessor does not access the watchdog timer within the time-out period of 100 ms or 1.6 s, a reset pulse is generated. After reset, the watchdog timer is disabled. The normal time-out period of 100 ms/1.6 s becomes effective after the first access to the watchdog timer.
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1 Specification EUROCOM-17-5xx 1.3.18 VMEbus Interface Each EUROCOM-17-5xx board offers VMEbus master and slave interfaces. Additionally, VMEbus system controller functions are available via the VMEbus gate array (VIC). 1.3.18.1 System Controller The EUROCOM-17-5xx features a full slot-one system controller, including SYSCLK, SYSRESET, bus time-out, IACK daisy chain driver, and a four level arbitration circuit. System controller capabilities are enabled by switch S3 in position 'SC' on the front panel.
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EUROCOM-17-5xx 1 Specification 1.3.19 Interrupt Sources The EUROCOM-17-5xx allows full utilization of both the powerful VMEbus interrupt structure and the 68040 CPU design. 1.3.20 Local Extension Bus The LEB port of the EUROCOM-17-5xx can carry slave-only, masteronly or master-slave boards. The IRQ line of the LEB is connected to VIC’s LIRQ5 input. The VIC has to be programmed to generate interrupts on level 2, because only level 2 IACK cycles are routed to the LEB. 1.3.
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1 Specification EUROCOM-17-5xx Configuration The configuration program is completely menu driven. The program interactively shows the configuration parameters and allows their modification: •I/O Configuration, e.g.: serial I/O, AT-keyboard, on-board video, baud rate, etc.
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EUROCOM-17-5xx 1.3.22 Connectors 1 Specification Table 3: 15-Pin VGA Connector (MONITOR PORT X1201) Pin 1 Signal (analog) Red (0.7 VPP / 1 V PP) or Red 3 (TTL) 2 Green (0.7 VPP / 1 VPP ) or Green 3 (TTL) 3 Blue (0.7 VPP / 1 VPP ) or Blue 3 (TTL) 4 nc or Blue 2 (TTL) 5 GND 6 GND 7 GND 8 GND 9 nc 10 GND 11 nc 12 nc or DIGCLK 13 HSync (TTL) prog. (pos./neg.) 14 VSync (TTL) prog. (pos./neg.
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1 Specification EUROCOM-17-5xx Table 6: 15-Pin AUI Connector (ETHERNET X801) Pin 20 Signal Description 1 CI-S Control In circuit Shield 2 CI-A Control In circuit A 3 DO-A Data Out circuit A 4 DI-S Data In circuit Shield 5 DI-A Data In circuit A 6 VC Voltage Common 7 CO-A Control Out circuit A 8 CO-S Control Out circuit Shield 9 CI-B Control Out circuit B 10 DO-B Data Out circuit B 11 DO-S Data Out circuit Shield 12 DI-B Data In circuit B 13 VP Voltage Plus 14 VS
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EUROCOM-17-5xx 1 Specification Table 7: Pin Assignment of VMEbus Connector (X101) Pin i Row A Row B Row C 1 D00 /BBSY D08 2 D01 /BCLR D09 3 D02 /ACFAIL D10 4 D03 /BG0IN D11 5 D04 /BG0OUT D12 6 D05 /BG1IN D13 7 D06 /BG1OUT D14 8 D07 /BG2IN D15 9 GND /BG2OUT GND 10 SYSCLK /BG3IN /SYSFAIL 11 GND /BG3OUT /BERR 12 /DS1 /BR0 /SYSRESET 13 /DS0 /BR1 /LWORD 14 /WRITE /BR2 AM5 15 GND /BR3 A23 16 /DTACK AM0 A22 17 GND AM1 A21 18 /AS AM2 A20
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1 Specification EUROCOM-17-5xx Table 8: Pin Assignment of Connector X102 Pin i 22 Signal Row A Signal Row B Signal Row C 1 SCSIDBP1 +5V SCSIDB1 2 SCSIDB0 GND SCSIDB3 3 SCSIDB2 Reserved SCSIDB5 4 SCSIDB4 A24 SCSIDB7 5 SCSIDB6 A25 SCSIDB9 6 SCSIDBP0 A26 SCSIDB11 7 SCSIDB8 A27 SCSIDB13 8 SCSIDB10 A28 SCSIDB15 9 SCSIDB12 A29 CIOPC3 10 SCSIDB14 A30 CIOPC1 11 CIOPC2 A31 CIOPA6 12 CIOPC0 GND CIOPA4 13 CIOPA7 +5V CIOPA2 14 CIOPA5 D16 CIOPA0 15 CIOPA3
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EUROCOM-17-5xx 1 Specification Table 9: Pin Assignment of the 32-bit LEB (X201) Pin i Row A Row B Row C Row D Row E 1 GND A08 A16 A24 Reserved 2 A01 A09 A17 A25 Reserved 3 A02 A10 A18 A26 Reserved 4 A03 A11 A19 A27 Reserved 5 A04 A12 A20 A28 D08 6 A05 A13 A21 A29 D09 7 A06 A14 A22 A30 D10 8 A07 A15 A23 A31 D11 9 D16 D24 FC0 SIZE0 D12 10 D17 D25 FC1 SIZE1 D13 11 D18 D26 FC2 +5V D14 12 D19 D27 /IRQ /CPU20 D15 13 D20 D28 /IACK
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1 Specification EUROCOM-17-5xx Table 10: Pin Assignment of 32-Bit Memory Module Connector (X202) Pin Description Pin Description 1A +12 V 26A LD5 2A GND 27A 3A LA0 4A Description Pin Description 1B +3V3 26B LD21 LD6 2B VCC 27B LD22 28A LD7 3B LA16 28B LD23 LA1 29A GND 4B LA17 29B VCC 5A LA2 30A LD8 5B LA18 30B LD24 6A LA3 31A LD9 6B LA19 31B LD25 7A LA4 32A LD10 7B LA20 32B LD26 8A LA5 33A LD11 8B LA21 33B LD27 9A LA6 34A LD12 9B
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EUROCOM-17-5xx 1 Specification Table 11: 50-Pin I/O Connector X102 (on ADAP-200 and ADAP-220) 1 49 2 50 Pin Dir Description Remark 1 8 I/O Not connected on ADAP-220, SCSIDB8 - SCSIDB15 on ADAP-200 9 - 10 13 I/O 14 - 15 22 I/O 23 - +5 V 24 - Serial Channel 4 GND2 25 - Serial Channel 4 GND1 26 - Serial Channel 4 not connected 27 I Serial Channel 4 CTS 28 O Serial Channel 4 TXD 29 O Serial Channel 4 RTS 30 I Serial Channel 4 RXD 31 - not connected 32 -
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1 Specification EUROCOM-17-5xx Table 12: SCSI Connector 8-bit X103 (on ADAP-200 and ADAP-220) Pin i 26 Description Pin Description 2 DB0 28 GND 4 DB1 30 GND 6 DB2 32 ATN 8 DB3 34 GND 10 DB4 36 BSY 12 DB5 38 ACK 14 DB6 40 RST 16 DB7 42 MSG 18 DB8 44 SEL 20 GND 46 CIO 22 GND 48 REQ 24 GND 50 I/O 26 TERM-PWR 1 2 49 50 All odd pins of the 50-pin SCSI connector except pin 25 are connected to ground. Pin 25 is left open.
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EUROCOM-17-5xx 1 Specification Table 13: SCSI Connector 16-bit X107 (on ADAP-220) Pin Description Pin Description 1 - 16 GND 50 GND 17 TERM 51 TERM 18 TERM 52 TERM 19 NC 53 NC 20 - 34 GND 54 GND 35 SCSIDB12 55 /SCSIATN 36 SCSIDB13 56 GND 37 SCSIDB14 57 /SCSIBSY 38 SCSIDB15 58 /SCSIACK 39 SCSIDP1 59 /SCSIRST 40 SCSIDB0 60 /SCSIMSG 41 SCSIDB1 61 /SCSISEL 42 SCSIDB2 62 /SCSIC/D 43 SCSIDB3 63 /SCSIREQ 44 SCSIDB4 64 /SCSII/O 45 SCSIDB5 65 SCSID
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1 Specification EUROCOM-17-5xx 1.4 Compatibility to the EUROCOM-17 The EUROCOM-17-5xx is built as an adequate substitute for the EUROCOM-17-1xx or EUROCOM-17-2xx. Nevertheless, some changes were necessary: Differences between EUROCOM-17-5xx and EUROCOM-17-1xx/2xx: •Address map slightly changed (see Chapter 3 ‘Programmers Reference’). •The graphics interface has changed. For detailed information, see Section 3.4 ‘Graphics Interface’. •4-bit overlay implemented (see Section 1.3.
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EUROCOM-17-5xx 1 Specification 1.5 Definition of Board Parameters 1.5.1 VMEbus •VMEbus interface according to specification ANSI/IEEE STD 1014-1987 (Rev. D1.
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1 Specification EUROCOM-17-5xx •Interrupter Options - Any one of I(n) where 1 ≤ n ≤ 7. •Address Range - programmable extended/standard/short I/O extended access (A31-A24 and mask) standard access (A23-A16 and mask) short I/O (A15 -A8) - Default: extended access 256 MB, short I/O 256 B 1.5.
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EUROCOM-17-5xx 1.5.5 Serial I/O 1 Specification •4 channels (50 b/s - 64 kb/s) •Keyboard: - MF2/AT mode 1.5.6 Parallel I/O •12-bit unbuffered TTL •CONV-300: - 12-bit buffered TTL - Centronics unidirectional 1.5.7 Video I/O •Dotclock: - 10 MHz - 120 MHz •1/2/4/8/15/16 bit/pixel •CLUT: - 256 colors out of 2 24 - 3x8-bit DAC •Video Resolution: - 640 x 480 - 1152 x 900 •Horizontal Frequencies: - 31.5 kHz to 70 kHz •Vertical Frequencies: - 60 Hz to 70 Hz 1.5.
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1 Specification 1.5.9 Environmental Conditions EUROCOM-17-5xx •Storage Temperature: -35°C to +85°C •Operating Temperature: 0°C to +60°C (non condensing) •Maximum Operating Humidity: 85% relative •Air temperature with forced air cooling of approx. 1 m/sec. 1.5.10 Power Requirements 32 (with all/max. options; approx.): +5 VDC ±5 % - 7.0 A max. 5.0 A typ. - 0.2 A max. 0.1 A typ. +12 VDC ±10 % - 0.2 A max. 0.1 A typ.
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EUROCOM-17-5xx 2 Installation 2 Installation 2.1 Introduction •Carefully remove the board from the shipping carton. - Save the original shipping container and packing material for storing or reshipping the board. Avoid touching integrated circuits except in an electrostatic free environment. Electrostatic discharge can damage circuits or shorten their lifetime. •Inspect the board for any shipping damage. If undamaged, the board can be prepared for system installation.
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2 Installation 2.1.2 Serial Interface Level Converter (SILC) EUROCOM-17-5xx The Serial Interface Level Converter (SILC) modules generally convert TTL-level signals generated or accepted by the SCC-2 to the appropriate signal levels for external transmission lines. SILC modules for RS 232C, RS 422 and RS 485 are available. The mechanical outline of the SILC modules allows the changeability of the different SILC modules on the EUROCOM-17-5xx.
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EUROCOM-17-5xx 2 Installation 2.1.4 Ethernet Installation A standard Ethernet/Cheapernet MAU or a CONV-500 Cheapernet/ 10BaseT MAU can be connected via AUI cable to the 15-pin AUI connector on the front panel of the EUROCOM-17-5xx. The length of the AUI cable is limited to 50 m. For connections up to about 2 m, flat cable can also be used. In order to avoid HF radiation, this cable should be shielded. 2.1.5 Pure 8-bit SCSI Installation A 8-bit SCSI bus can be connected to X103 of ADAP-200/220.
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2 Installation EUROCOM-17-5xx Figure 4: Installation Diagram Centronics Port Status Display SCSI Port Slave Address Operating Mode System Controller Reset / Status Parallel I/O (TTL) Monitor (VGA) Port Keyboard Mouse / Serial (RS 232) Port RS 232 Port Ethernet RS 232 Ports (RS 422, RS 485) 36 Hardware Manual
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EUROCOM-17-5xx 2 Installation 2.2 Default Board Setting Table 14: Default Settings Jumpers/Switches Position Description J301 1-2 VIC68 J1201 1-2 Digclk, see Section 2.3.1 ‘ Digclk Invertion (J1201)’ J1202 open TTL graphic outputs disabled, see Section 2.3.2 ‘ Enable TTL Video (J1202)’ J1401 closed J1601 open No programming voltage for Flash EPROM, see Section 2.3.4 ‘ Flash EPROM Programming Voltage (J1601)’ J1605 1-2 See Section 2.3.
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2 Installation EUROCOM-17-5xx Figure 5: Location of Jumpers (Bottom View) 38 Hardware Manual
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EUROCOM-17-5xx 2 Installation Figure 6: Location of Jumpers, Interface Connectors and Switches Hardware Manual 39
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2 Installation EUROCOM-17-5xx 2.3 Jumpers and Switches This section lists all features user-selectable by jumpers and switches. For details, refer to the appropriate descriptions identified in parentheses. All settings on a dark grey background ( ) indicate default settings. The EUROCOM-17-5xx operates as single board computer in this configuration. There are only very few jumpers on the EUROCOM-17-5xx which typically need no changes after shipping. All other parameters are software programmable.
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EUROCOM-17-5xx 2.3.3 Watchdog Period (J1401) 2 Installation J1401 is to select between 100 ms and 1.6 s watchdog periods. J1401 is a soldering jumper. Table 17: J1401 (Watchdog Period) 2.3.4 2.3.5 Flash EPROM Programming Voltage (J1601) Pin 1 Connection of EPROM (J1605) Jumper J1401 Function open Watchdog period 1.
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2 Installation 2.3.7 Snooping of Secondary CPU (J1801) EUROCOM-17-5xx If snooping of the secondary CPU is enabled via the snoop control register SNCR, the /MI output of the secondary CPU must be observed (J1801 in position 2-3). If snooping of the secondary CPU is disabled or in single processor systems, /MI of the secondary CPU can be ignored (J1801 in position 1-2). Table 21: J1801 (Snooping of Secondary CPU) Jumper J1801 2.3.
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EUROCOM-17-5xx 2.3.9 Switches 2 Installation Two rotary hex switches (S901 and S902), the system controller switch (S3) and the reset switch (S4) are all located on the front panel. If the system controller switch (S3) is switched to the 'SC' position, the board acts as VMEbus system controller.
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2 Installation EUROCOM-17-5xx Table 23: Hex Switch S901 (VMEbus Slave Address) Hex Switch S901 i 44 VMEbus Base Address A32 A24 A16 F $F000.0000 disabled $F000 E $E000.0000 disabled $E000 D $D000.0000 disabled $D000 . . . . 1 $1000.0000 disabled $1000 0 Use configuration value A24 access must be enabled separately. For a detailed description, see Section 3.2.3 ‘Address Translation’.
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EUROCOM-17-5xx 2.3.9.2 Hardware Configuration (S902) 2 Installation The lower switch (S902) defines the configuration source and the operation mode. For switch position 0, 1, RMon enters an interactive mode. If switch S902 is in position 8 to F, the program located in the user EPROM is called. Table 24: Hex Switch S902 (Hardware Configuration) Hex Switch S902 i 2.3.9.
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2 Installation 46 EUROCOM-17-5xx Hardware Manual
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EUROCOM-17-5xx 2 Installation 2 Installation 2.1 Introduction •Carefully remove the board from the shipping carton. - Save the original shipping container and packing material for storing or reshipping the board. Avoid touching integrated circuits except in an electrostatic free environment. Electrostatic discharge can damage circuits or shorten their lifetime. •Inspect the board for any shipping damage. If undamaged, the board can be prepared for system installation.
PAGE 78
2 Installation 2.1.2 Serial Interface Level Converter (SILC) EUROCOM-17-5xx The Serial Interface Level Converter (SILC) modules generally convert TTL-level signals generated or accepted by the SCC-2 to the appropriate signal levels for external transmission lines. SILC modules for RS 232C, RS 422 and RS 485 are available. The mechanical outline of the SILC modules allows the changeability of the different SILC modules on the EUROCOM-17-5xx.
PAGE 79
EUROCOM-17-5xx 2 Installation 2.1.4 Ethernet Installation A standard Ethernet/Cheapernet MAU or a CONV-500 Cheapernet/ 10BaseT MAU can be connected via AUI cable to the 15-pin AUI connector on the front panel of the EUROCOM-17-5xx. The length of the AUI cable is limited to 50 m. For connections up to about 2 m, flat cable can also be used. In order to avoid HF radiation, this cable should be shielded. 2.1.5 Pure 8-bit SCSI Installation A 8-bit SCSI bus can be connected to X103 of ADAP-200/220.
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2 Installation EUROCOM-17-5xx Figure 4: Installation Diagram Centronics Port Status Display SCSI Port Slave Address Operating Mode System Controller Reset / Status Parallel I/O (TTL) Monitor (VGA) Port Keyboard Mouse / Serial (RS 232) Port RS 232 Port Ethernet RS 232 Ports (RS 422, RS 485) 36 Hardware Manual
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EUROCOM-17-5xx 2 Installation 2.2 Default Board Setting Table 14: Default Settings Jumpers/Switches Position Description J301 1-2 VIC68 J1201 1-2 Digclk, see Section 2.3.1 ‘ Digclk Invertion (J1201)’ J1202 open TTL graphic outputs disabled, see Section 2.3.2 ‘ Enable TTL Video (J1202)’ J1401 closed J1601 open No programming voltage for Flash EPROM, see Section 2.3.4 ‘ Flash EPROM Programming Voltage (J1601)’ J1605 1-2 See Section 2.3.
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2 Installation EUROCOM-17-5xx Figure 5: Location of Jumpers (Bottom View) 38 Hardware Manual
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EUROCOM-17-5xx 2 Installation Figure 6: Location of Jumpers, Interface Connectors and Switches Hardware Manual 39
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2 Installation EUROCOM-17-5xx 2.3 Jumpers and Switches This section lists all features user-selectable by jumpers and switches. For details, refer to the appropriate descriptions identified in parentheses. All settings on a dark grey background ( ) indicate default settings. The EUROCOM-17-5xx operates as single board computer in this configuration. There are only very few jumpers on the EUROCOM-17-5xx which typically need no changes after shipping. All other parameters are software programmable.
PAGE 85
EUROCOM-17-5xx 2.3.3 Watchdog Period (J1401) 2 Installation J1401 is to select between 100 ms and 1.6 s watchdog periods. J1401 is a soldering jumper. Table 17: J1401 (Watchdog Period) 2.3.4 2.3.5 Flash EPROM Programming Voltage (J1601) Pin 1 Connection of EPROM (J1605) Jumper J1401 Function open Watchdog period 1.
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2 Installation 2.3.7 Snooping of Secondary CPU (J1801) EUROCOM-17-5xx If snooping of the secondary CPU is enabled via the snoop control register SNCR, the /MI output of the secondary CPU must be observed (J1801 in position 2-3). If snooping of the secondary CPU is disabled or in single processor systems, /MI of the secondary CPU can be ignored (J1801 in position 1-2). Table 21: J1801 (Snooping of Secondary CPU) Jumper J1801 2.3.
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EUROCOM-17-5xx 2.3.9 Switches 2 Installation Two rotary hex switches (S901 and S902), the system controller switch (S3) and the reset switch (S4) are all located on the front panel. If the system controller switch (S3) is switched to the 'SC' position, the board acts as VMEbus system controller.
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2 Installation EUROCOM-17-5xx Table 23: Hex Switch S901 (VMEbus Slave Address) Hex Switch S901 i 44 VMEbus Base Address A32 A24 A16 F $F000.0000 disabled $F000 E $E000.0000 disabled $E000 D $D000.0000 disabled $D000 . . . . 1 $1000.0000 disabled $1000 0 Use configuration value A24 access must be enabled separately. For a detailed description, see Section 3.2.3 ‘Address Translation’.
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EUROCOM-17-5xx 2.3.9.2 Hardware Configuration (S902) 2 Installation The lower switch (S902) defines the configuration source and the operation mode. For switch position 0, 1, RMon enters an interactive mode. If switch S902 is in position 8 to F, the program located in the user EPROM is called. Table 24: Hex Switch S902 (Hardware Configuration) Hex Switch S902 i 2.3.9.
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EUROCOM-17-5xx 3 Programmers Reference 3 Programmers Reference 3.1 Address Map The EUROCOM-17-5xx is designed to utilize the entire 4 GB address range of the 68040 chip. Using the address modifier of the VMEbus, the address range may be enlarged by subdivision into data and program areas and/or user and supervisor areas. The EUROCOM-17-5xx recognizes two address areas: the local address space and the global VMEbus address space.
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3 Programmers Reference EUROCOM-17-5xx Accesses to reserved local RAM areas will generate a bus error. Table 27: Local I/O Address Assignment for EUROCOM-17-5xx Address 48 Device Size Access $FEC0.0000 - $FEC0.7FFF VIC (D0..7) byte read/write $FEC0.8000 - $FEC0.FFFF VMEbus Decoder (D0..31) see Section 3.2.2 ‘ RAM Access from the VMEbus’ lword write $FEC1.0000 - $FEC1.FFFF User CIO byte read/write $FEC2.0000 - $FEC2.FFFF NVRAM/RTC byte read/write $FEC3.0000 - $FEC3.
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EUROCOM-17-5xx 3 Programmers Reference 3.2 DRAM 3.2.1 RAM Access from the Local CPUs i 3.2.2 RAM Access from the VMEbus The base address of the DRAM is fixed to $0000.0000. After reset, the basic EPROM is mapped to address $0000.0000. After some initialization the firmware enables the DRAM at $0000.0000 via PA5 of the system CIO.
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3 Programmers Reference EUROCOM-17-5xx The ICF1 decoder compares A15 to A8 of the VMEbus with the SBR bits 15 to 8. If a SMR mask bit is set, then the corresponding VMEbus address bit is ‘don’t care’. For full support of the VIC’s interprocessor communication features, the EUROCOM-17-5xx has a second A16 decoder called ICF2 decoder. The ESR register allows separate enabling of the four comparators. Table 29: Enable Slave Register Layout Reg. Address ESR $FEC5.C000 7 ...
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EUROCOM-17-5xx 3 Programmers Reference Unfortunately the address translation exists only once for the three address sources (VMEbus, LEB, ILACC). This leads to some restrictions when the DRAM/VRAM is accessed by A24 addressing from the VMEbus or the LEB. In this case only parts of the DRAM/VRAM can be reached by VMEbus A32 addressing or the ILACC. Example: 1 MB slave window size for VMEbus A24 addressing at $C0.0000 to the first MB of the DRAM: MBAR ASR SBR SMR = $0000.0000 = $FFF0.0000 = $xxC0.
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3 Programmers Reference 3.2.6 RAM Access from ILACC EUROCOM-17-5xx The AM79C900 Ethernet Controller uses DMA transfer cycles to transfer commands, data and status information to and from the DRAM. 3.3 VMEbus Interface Each EUROCOM-17-5xx has a VMEbus master and a VMEbus slave interface. Additionally, VMEbus system controller functions are available via the VMEbus gate array (VIC) used on the EUROCOM-17-5xx board. 3.3.
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EUROCOM-17-5xx 3.3.2 VMEbus Master Interface 3 Programmers Reference The master interface of the EUROCOM-17-5xx board supports 8, 16, and 32-bit data transfer cycles in A32, A24, and A16 addressing modes. For a short overview, see Section 1.5 ‘Definition of Board Parameters’. 3.3.2.
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3 Programmers Reference 3.3.2.4 VMEbus Block Transfer Option EUROCOM-17-5xx The EUROCOM-17-5xx board supports master/slave block transfer cycles. This is done by the MOVEM.L operation of the CPU, or by the local DMA device in the VIC. The data size is restricted to D32 and may cross 256 byte boundaries if the slave is also capable of boundary crossing. Several options within the VIC chip allow to generate different block transfer cycle types.
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EUROCOM-17-5xx 3.3.2.5 A16 Slave Interface (ICMS, ICGS) 3 Programmers Reference A very useful feature of the VIC is a set of registers and switches for message passing or event signaling. There are eight bytewide general-purpose interprocessor communication registers accessible from the VMEbus or the local bus (CPU). •Registers 0 to 4 are general-purpose dual-port registers. •Register 5 is a dual-port read-only ID register to identify the VIC and its revision level.
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3 Programmers Reference EUROCOM-17-5xx Table 30: Intercommunication Register Location on VMEbus Register Type A07 06 05 04 03 02 01 AM5..0 Interprocessor Communication Registers X X 0 0 # # # $2D Interprocessor Communication Global Switches X X 0 1 0 # # $2D Interprocessor Communication Module Switches X X 1 0 0 # # $2D or $29 X : don’ t care. # : selects register/switch number. For further information, refer to the VIC068 data sheet.
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EUROCOM-17-5xx 3 Programmers Reference 3.4 Graphics Interface 3.4.1 Video Graphics Address Map Table 31: Video Address Map Address Access to $0FC0.0000$0FCF.FFFF Video Memory 1 MB $0FE0.0000$0FEF.FFFF Port Size (Bit) Access Type 32/16/8 read/write burst Overlay Memory 0.5 MB 32/16 read/write burst $FEC4.0000$FEC4.0007 Direct Register of Bt445 8 read/write $FEC4.0008$FEC4.7FFF Mirrored Direct Register of Bt445 $FEC4.8000$FEC4.8007 Address and Sync Generator 8 write only $FEC4.
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3 Programmers Reference EUROCOM-17-5xx Table 32: Register of Bt445 Direct Address Indirect Address Name Description $FEC4.0000 $XX BT_ADR Address Register $FEC4.0001 $00-$FF BT_CLUT Primary Color Palette RAM $FEC4.0002 $00 IDR ID Register $01 RR Revision Register $04 RER Read Enable Register $05 BER Blink Enable Register $06 CR0 Command Register 0 $07 TR0 Test Register 0 $08-$FF $FEC4.0003 $00-$0F Reserved BT_OVLU $10-$FF Reserved $FEC4.0004 $XX Reserved $FEC4.
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EUROCOM-17-5xx 3 Programmers Reference Table 32: Register of Bt445 (Continued) Direct Address Indirect Address Name Description $FEC4.0005 $1A ODEC Overlay Display Enable Control $1B OBER Overlay Blink Enable Register $1C-$1F Reserved Reserved $20 CMSBP Cursor MSB Position $21 CWC Cursor Width Control $22 CDEC Cursor Display Enable Control $23 CBER Cursor Blink Enable Register $24-$FF $FEC4.
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3 Programmers Reference EUROCOM-17-5xx Table 33: Register of Address and Sync Generator Address Name Description $FEC4.8000 TRLSB Transfer Address Least Significant Byte $FEC4.8001 TRMIB Transfer Address Middle Byte $FEC4.8002 TRMSB Transfer Address Most Significant Byte $FEC4.8003 Reserved $FEC4.8004 TRINC Address Increment (pitch) in 128 byte steps: $01 = 128 bytes $02 = 256 bytes $03 = 384 bytes .. $0F = 1920 bytes $00 = 2048 bytes $FEC4.8005 GRMODE Bit No.
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EUROCOM-17-5xx 3 Programmers Reference 3.4.3 Address Generator The address generator has five write-only registers. The three transfer address registers TRLSB, TRMIB, and TRMSB determine the address of the first displayed pixel of each frame. When the transfer increment register TRINC is programmed to a value larger than the line length and synchronous transfer mode is selected in the graphics mode register GRMODE, the address transfer register can be used to implement horizontal and vertical paning.
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3 Programmers Reference EUROCOM-17-5xx Figure 8: Pixel Model Address $x0 Pixel n Address $x+1 Address $x+2 Address $x+3 Pixel n+1 Pixel n+2 Pixel n+3 D31 D0 longword boundary For 1/2/4 bit per pixel operation, the most significant part of each byte represents the leftmost pixel and the least significant part represents the rightmost pixel on the screen. 3.4.6 Overlay Memory The overlay memory has the same structure as the video memory. It starts at $0FE0.
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EUROCOM-17-5xx 3 Programmers Reference •In interlaced mode bit 2 of the TRMIB register can be used to swap the contents of the two frames. •For interlaced operation REG4 of the LM1882 must be even. •For interlaced operation with an odd number of lines (CCIR, EIA), the first and the last displayed line should be set to black because they are only displayed half. •Interlaced mode can only be used when the SPLIT bit in the GRMODE register is clear.
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3 Programmers Reference EUROCOM-17-5xx 3.5 Ethernet Interface (802.3/10base5) The ILACC’s internal registers are selected by writing the corresponding register number to address $FEC6.8006 and accessed at address $FEC6.8002. Both addresses must be accessed with word-size instructions. After initialization and starting, the ILACC operates without any CPU interaction. It transfers prepared data, receives incoming packets and stores them into reserved memory locations.
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EUROCOM-17-5xx 3 Programmers Reference 3.6 CIO Counter / Timers The EUROCOM-17-5xx offers six independent, programmable 16-bit counter / timers integrated in two CIOs. Three of these counters, located in the user CIO ($FEC1.0000), can be used as general-purpose devices with up to four external access lines per counter / timer (count input, output, gate, and trigger). Port A and C of this CIO are connected to X102 for user application. Refer to Table 8: ‘Pin Assignment of Connector X102’.
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3 Programmers Reference EUROCOM-17-5xx On default setting, the system CIO, user CIO and the CL-CD2401 are routed to the same IRQ level (LIRQ6) of the VIC. The CL-CD2401 has the highest priority. A special feature of the EUROCOM-17-5xx is the programmable interrupt level of the CIOs and the graphic frame interrupt. So, the CIOs can be routed to an other interrupt level as the serial controller CL-CD2401. The CIO interrupt level register (at address $FEC5.
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EUROCOM-17-5xx 3 Programmers Reference 3.7 Serial I/O The EUROCOM-17-5xx offers four serial I/O lines, implemented by a CL-CD2401 Multi-Protocol Controller (MPC). C1 and C2 are hardwired to feature RS 232 two-wire (C1) and four-wire (C2) hardware handshake mode, while C3 and C4 use removable serial interface level converters (SILC). As shipped, two RS 232 level converter SILCs are installed featuring hardware handshake as well as XON/XOFF protocol.
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3 Programmers Reference EUROCOM-17-5xx The local interrupt control register 6 (LIRQ6) of the VIC has to be programmed for an active low, level-sensitive input. The vectors are supplied by the MPC. The VIC has to be programmed to generate interrupts on level 5 to the CPU. Only CPU IACK level 5 cycles are routed to the MPC. i 68 For polled operation, the MPC can be switched to IACK context by reading address $FEC6.6000 - $FEC6.7FFF.
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EUROCOM-17-5xx 3 Programmers Reference 3.8 Watchdog Timer The watchdog timer installed on the EUROCOM-17-5xx monitors the activity of the microprocessor. If the microprocessor does not write location $FEC5.0000 within the time-out period of 100 ms (min. 70 ms; max. 140 ms) or 1.6 s (±30%), a reset pulse is generated. After reset, the watchdog timer is disabled. The normal time-out period of 100 ms becomes effective after the first write access to address $FEC5.0000.
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3 Programmers Reference EUROCOM-17-5xx 3.9 Keyboard Interface The keyboard interface is designed to support PS/2 compatible keyboards. This interface receives data from and transmits data to the keyboard under interrupt control. The keyboard interface consists of two registers: the data register and the control/status register. Table 41: Address Assignment of Keyboard Controller Registers Address Description Width [b] $FEC6.0000 Data Register 8 $FEC6.
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EUROCOM-17-5xx 3 Programmers Reference Table 42: Keyboard Control/Status Register CSR Readable bits D7 D0 - - - - - - RBF TBE Name: Control/Status Register Shortname: CSR Address: $FEC6.0001 TBE - Transmit Buffer Empty 0 The transmit buffer is full and data transmission is in progress. Writing data to the data register with TBE clear will destroy the data byte which is currently transmitted. 1 The transmit buffer is empty. Data can be written into the data register.
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3 Programmers Reference EUROCOM-17-5xx 3.10 IOC-2 ELTEC’s Input/Output Controller (IOC-2) is an ASIC intended to maximize the performance of ELTEC’s CPU boards. The IOC-2 is specially designed as data/address bridge between a 68040-type local bus and VIC068/064 to support fast VMEbus master/slave block transfers. A second main function is a universal programmable I/O bus interface with an appropriate address decoder. 3.10.
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EUROCOM-17-5xx 3 Programmers Reference Table 43: Register Map (Continued) Offset Addr. Symbol Name Reset Value $7002C IODCR10 I/O Device Control Register 10 $0000.0000 $70030 IODCR11 I/O Device Control Register 11 $0000.0000 $70034 IODCR12 I/O Device Control Register 12 $0000.0000 $70038 IOIACR I/O IACK Control Register $0000.0000 $7003C -- reserved $70040 EBAR0 EPROM Begin Address Register 0 $0000.0000 $70044 EMAR0 EPROM Mask Register 0 $0000.
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3 Programmers Reference EUROCOM-17-5xx 3.11 SCSI Interface A Small Computer System Interface (SCSI) controller is built around a NCR53C720 chip. The full specification (ANSI K3T 9.2) is implemented, supporting all standard SCSI features including arbitration, disconnect, reconnect, and parity. 3.11.1 SCSI Controller The interrupt request line (IRQ) of the SCSI controller is connected to the LIRQ3 input of the VIC.
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EUROCOM-17-5xx 3 Programmers Reference 3.12 Status Display The EUROCOM-17-5xx features a seven-segment display on the front panel and displays hexadecimal values from 0 to F. This status display is designed as read/write register and uses the least significant nibble of the byte. As an example, the following sequence moves a 'D' in the hex display: move.b #$0D,$FEC30000 The left decimal point of the hex display is used as watchdog indicator.
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3 Programmers Reference EUROCOM-17-5xx 3.13 Battery-Backed Parameter RAM and Real-Time Clock The real-time clock is designed with the MK 48T12 or MK 48T18 timekeeper RAM from SGS Thomson or DS1644 from Dallas. The chip combines a 2KBx8 (8KBx8, 32KBx8) CMOS SRAM (parameter RAM) a bytewide accessible real-time clock, a crystal, and a long life lithium battery, all in one package. The MK 48Txx devices have a battery lifetime of approximetly 3.7 years when the clock oscillator is running.
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EUROCOM-17-5xx 3.13.2 Real-Time Clock 3 Programmers Reference The clock features BCD-coded year, month, day, hours, minutes, and seconds as well as a software controlled calibration. For lifetime calculations of the battery, please refer to the data sheet. Access to the clock is as simple as conventional bytewide RAM access because the RAM and the clock are combined in the same chip. Table 45: Address Assignment of the Real-Time Clock MK 48T12 Address Description $FEC2.
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3 Programmers Reference EUROCOM-17-5xx 3.15 Reset During power-up or after actuation of the reset switch (S4), /RESET is held low for approximately 1 s. If the system controller switch (S3) is in the 'SC' position, the VMEbus is also reset because the VIC is configured as the VMEbus system controller. Otherwise SYSRESET from the VMEbus is an input.
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EUROCOM-17-5xx 3 Programmers Reference 3.16 Bus Time-Out The EUROCOM-17-5xx features two independent, softwareprogrammable bus time-out modules; one for the local time-out and one for the VMEbus time-out. Both time-out modules are located in the VIC and are programmed by writing the transfer time-out register ($FEC0.10A3). The time-out period is programmable from 4 µs to 480 µs. Local time-out is not generated when waiting for VMEbus mastership. This is programmable within the VIC chip.
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3 Programmers Reference EUROCOM-17-5xx 3.17 System Control Register (SCR) The EUROCOM-17-5xx features several status and control bits to monitor and change the system control signals. These are implemented using port lines of the system CIO. Reset initializes all ports as input. The default values are set during the RMon initialization routine. Table 47: System Control Register Layout (System CIO) i 80 Bit No.
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EUROCOM-17-5xx 3 Programmers Reference 3.18 Interrupt Sources All seven priority levels of the VMEbus are implemented. The local modules can be served by interrupts without restricting the VMEbus interrupt capacity. The interrupt handler is a part of the VIC gate array. This device contains seven registers to handle seven VMEbus interrupt sources. Each IRQ line on the VMEbus is enabled and disabled separately.
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3 Programmers Reference EUROCOM-17-5xx Table 48: VIC Interrupt Priority Scheme IRQ Source Generated CPU Level Vector supplied by LIRQ7 ILACC 3 VIC Error Group IRQ ACFAIL from VMEbus 7 VIC Write Post Fail 7 VIC Arbitration Time-out 7 VIC SYSFAIL from VMEbus 7 VIC 5 1) CL-CD2401 System CIO medium priority 5 1) System CIO User CIO lower priority 5 1) User CIO LIRQ5 LEB 2 1) LEB LIRQ4 Video Frame Inactive 5 VIC LIRQ3 SCSI Controller 2 VIC LIRQ2 Clock Tick Timer of V
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EUROCOM-17-5xx 3.18.1 Local Interrupt Sources 3 Programmers Reference The EUROCOM-17-5xx has eight local interrupt sources connected to six VIC inputs (LIRQ1, LIRQ3 to LIRQ7).
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3 Programmers Reference 3.18.2 VMEbus Interrupt Sources EUROCOM-17-5xx Individual interrupt levels are masked dynamically under software control by programming the appropriate VMEbus interrupt control register (ICR1 to ICR7) of the VIC. This feature allows easy implementation of multiprocessor systems. The VMEbus interrupt requests are always active low and level-sensitive. All VMEbus IRQs are disabled after the initialization of RMon. To change this, use the RMon setup menu.
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EUROCOM-17-5xx 3 Programmers Reference 3.19 Secondary CPU Support ! The revision register must contain a dual-CPU order number to enable secondary CPU support. On single-CPU boards, the second CPU can be installed, but may not be usable. So, installing a second CPU must be done only at the factory! The secondary CPU is controlled via the CPU2CON at $FEC5.8000.
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3 Programmers Reference 3.19.2 Interrupting the Primary CPU EUROCOM-17-5xx The primary CPU is interrupted by the secondary CPU by writing bits 0-3 of the VIC’s interprocessor communication switch register ($FEC0.105F). A clear to set transition of a bit interrupts the primary CPU when the corresponding bit in the ICMS interrupt control register ($FEC0.1047) is clear (see also VIC data sheet). Table 50: CPU2CON As Seen by Primary CPU Bit Pos.
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EUROCOM-17-5xx 3 Programmers Reference Table 51: CPU2CON As Seen by Secondary CPU Bit Pos. Name Read/ Write Description 7 MIPEND read Mailbox Interrupt Pending 0 = interrupt acknowledged by secondary CPU 1 = mailbox interrupt pending 6 CPUID read CPU Identification always 0 when read by secondary CPU 5 VICIRQ read VIC Interrupt Request 0 = no interrupt from VIC clock 1 = interrupt from VIC clock 2 1 0 SICF2 SICF1 SICF0 write write write Secondary CPU Interrupt Control Function 0-2.
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3 Programmers Reference 3.19.4 Cache Coherency and Snooping EUROCOM-17-5xx To maintain cache coherency in a multi master system, the ‘040 has the capability of snooping. Snooping can be enabled via snoop control register at $FEC5.E000 (write only). EUROCOM-17-5xx snooping: Table 52: Snoop Control Register Layout for EUROCOM-17-5xx Register Address SNCR $FEC5.
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EUROCOM-17-5xx i i 3 Programmers Reference The snoop control register is write only. So the user must implement some mechanism to avoid that one CPU accidently alters the snooping mode of the other CPU. Snooping of the secondary CPU has to be enabled only if J1802 is set to position 2-3. Enabling snooping of the secondary CPU with J1802 in position 1-2 will cause erratic behavior of the secondary CPU.
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3 Programmers Reference EUROCOM-17-5xx Because the FRAM can only be handled via an I2C bus protocol, data should only be modified using the implemented RMon utilities. Therefore, see RMon Documentation. The FRAM is controlled in detail by the signals SDIO and SCLK. These signals can be set via a register at address $FEC5.4000. Table 55: I2C Control Register Layout Register Address I2C $FEC5.
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EUROCOM-17-5xx 3 Programmers Reference 3.21 Indivisible Cycle Operation 3.21.1 Deadlock Resolution When a CPU performs a locked cycle to the '020 bus (e.g. TAS to the VMEbus) and someone wants to access the '040 bus from the '020 bus (e.g. slave access from VMEbus to the local RAM) there is a deadlock situation. On normal reads or writes such a deadlock is resolved by sending a retry acknowledge to the CPU.
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3 Programmers Reference 92 EUROCOM-17-5xx Hardware Manual
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EUROCOM-27 Appendix Appendix Hardware Manual 91
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A.1 Mnemonics Chart EUROCOM-27 A.1 Mnemonics Chart This is the same mnemonics chart that can be found in the VMEbus Specification. A.1.1 A.1.2 Addressing Capabilities Data Transfer Capabilities When the following mnemonic is applied to a board ...
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EUROCOM-27 A.1 Mnemonics Chart Slave Data Transfer When the following mnemonic is applied to a board ... SD8(O) SRMW(O) It means that the SLAVE has the following data transfer capabilities: D08(O) D08(O) D16 D32 UAT BLT RMW X X X SD8 SBLT8 SRMW8 SALL8 X X X X SD16 SBLT16 SRMW16 SALL16 X X X X X X X X SD32 SBLT32 SRMW32 SALL32 X X X X X X X X X X X X X X X X X X X X X X X X X X Location Monitor Data Transfer When the following mnemonic is applied to a board ...
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A.2 Address Modifiers on VMEbus EUROCOM-27 A.
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EUROCOM-27 A.
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EUROCOM-27 A.3 Index A.3 Index A Address Map . . . . . . . . . . . . . . . . . . . . . . . . . 45 Address Modifier Source . . . . . . . . . . . . . . . 51 Address Translation . . . . . . . . . . . . . . . . . . . 48 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 71 B Bandwidth of the RAM . . . . . . . . . . . . . . . . . . 9 basic EPROM . . . . . . . . . . . . . . . . . . . . . . . . 10 baud rate generator . . . . .
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A.3 Index (Continued) P Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . 14, 34 Parameter RAM . . . . . . . . . . . . . . . . . . . . 14, 74 Power-On Initialization . . . . . . . . . . . . . . . . . 17 PS/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 R RAM . . . . . . . . . . . . . . . . . . . . . . . 9, 47, 49, 50 RAM Mirror . . . . . . . . . . . . . . . . . . . . . . . . . 49 RBF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Read-Modify-Write Cycles .
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EUROCOM-27 A.4 References A.4 References For more information, we recommend the following additional literature: MC68(EC/LC)040 M68040UM/AD Microprocessors User’s Manual Motorola Ltd.; European Literature Centre; 88Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England Further specifications and extracts of data sheets are available with the Service Manual. For ordering information, refer to ‘Related Products’, page X.