Service manual
Schematic Diagrams
B - 4 Processor 2/7
B.Schematic Diagrams
Processor 2/7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_SSC_P
PCH_SSC_N
BUF_CPU_RST#
CPUDRAMRST#
H_PROCHOT#_R
CPU_RST#
XDP_DBR_R
CPU_RST_N
SKTOCC#
XDP_BPM3
XDP_BPM7
XDP_DBR_R
XDP_TDO_R
XDP_TMS
XDP_TRST#
XDP_TCLK
XDP_TDI_R
XDP_PREQ#FC_AK31
H_CPUPWRGD
VDDPWRGOOD_RPMSYS_PWRGD_BUF
H_PROCHOT#
FC_AK31
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TCLK
XDP_TRST#
XDP_TMS
H_CATERR#
CPUDRAMRST#
PMSYS_PWRGD_BUF
XDP_TDO_R
XDP_TDI_R
XDP_PREQ#
PWRGD_BUF
XDP_BPM2
XDP_BPM6
XDP_PRDY#
H_CPUPWRGD
BUF_CPU_RST#
H_PROCHOT#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
C_D_RST#
XDP_BPM1
XDP_BPM5
XDP_TDO_R
XDP_BPM0
XDP_BPM4
CPU_RST_N
1.05V_LAN_M
VCCIO_OUT
V_VDDQ_DIMM
1.05V_LAN_M
3.3VS
VCCIO_OUT
V_VDDQ_DIMM
1.05V_LAN_M
1.05V_LAN_M
1.05V_LAN_M6,17,18,29,35,40,41
V_VDDQ_DIMM4,6,9,10,39
DDR3_DRAMRST# 9,10
DRAMRST_CNTRL 4,12
CLK_EXP_P19
CLK_EXP_N19
H_PROCHOT#40
PCH_SSC_N19
PCH_SSC_P19
H_CPUPWRGD15
H_PROCHOT_EC25
BUF_PLT_RST#14,28,33
CPU_RST_N15
VDD311,12,13,15,16,17,18,19,20,21,22,25,27,29,33,34,35,37,38,39,41,42
VCCIO_OUT5,6,40
H_PECI15,25
PCH_CK_DP_N19
PCH_CK_DP_P19
H_THRMTRIP#15
PM_DRAM_PWRGD13
SUSB23,24,34,38,39
3.3VS5,9,10,11,12,13,14,15,17,18,19,21,24,25,26,27,28,30,31,33,34,35,36,40
H_PM_SYNC13
Title
Size Document Number Rev
Date: Sheet
of
6-71-A11S0-D02
1.0
[03] PROCESSOR 2/7
A3
346Monday, August 19, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-A11S0-D02
1.0
[03] PROCESSOR 2/7
A3
346Monday, August 19, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-A11S0-D02
1.0
[03] PROCESSOR 2/7
A3
346Monday, August 19, 2013
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
PU/PD for JTAG signals
CAD Note: Capacitor need to be placed
close to buffer output pin
S3 circuit:- DRAM_RST# to memory
should be high during S3
DDR3 Compensation Signals
TRACE WIDTH 10MIL, LENGTH <500MILS
Processor Pullups/Pull downs
S3 circuit:- DRAM PWR GOOD logic
Haswell Processor 2/7 ( MISC,JTAG,CLK )
BSS138 ( VGS 1.5V )
Buffered reset to CPU
R68 51_04R68 51_04
R49 *10mil_shortR49 *10mil_short
R32
1K_04
R32
1K_04
R56 100_1%_04R56 100_1%_04
R57 75_1%_04R57 75_1%_04
R23 *51_04R23 *51_04
C39
47P_50V_NPO_04
C39
47P_50V_NPO_04
R27 62_04R27 62_04
R47 56_1%_04R47 56_1%_04
R48 *51_04R48 *51_04
R22 *51_04R22 *51_04
PWR
DDR3L
MISC
THERMAL CLOCK
JTAG
Haswell rPGA EDS
2 OF 9
U40B
PZ94721-3622
PWR
DDR3L
MISC
THERMAL CLOCK
JTAG
Haswell rPGA EDS
2 OF 9
U40B
PZ94721-3622
FC_AK31
AK31
PM_SYNC
AT28
PWRGOOD
AL34
BPM_N_7
AP28
BPM_N_6
AP29
BPM_N_5
AN28
BPM_N_4
AP30
BPM_N_3
AP31
BPM_N_2
AN29
BPM_N_1
AN31
BPM_N_0
AR30
DBR
AP33
TDO
AL33
TDI
AM31
TRST
AM33
TMS
AN33
TCK
AM34
PREQ
AT29
PRDY
AR29
SM_DRAMRST
AN3
SM_RCOMP_2
AP2
SM_RCOMP_1
AR3
SM_RCOMP_0
AP3
BCLKP
E26
BCLKN
D26
SSC_DPLL_REF_CLKP
E27
SSC_DPLL_REF_CLKN
F27
DPLL_REF_CLKP
H28
DPLL_REF_CLKN
G28
PROCHOT
AM30
PECI
AR27
CATERR
AN32
SKTOCC
AP32
PLTRSTIN
AT26
SM_DRAMPWROK
AC10
THERMTRIP
AM35
R26
100K_04
R26
100K_04
R45 *0_04R45 *0_04
R42
3.32K_1%_04
R42
3.32K_1%_04
R59 100_1%_04R59 100_1%_04
C40
0.047u_10V_X7R_04
C40
0.047u_10V_X7R_04
R38
*1K_1%_04
R38
*1K_1%_04
R29
1.82K_1%_04
R29
1.82K_1%_04
R67 51_04R67 51_04
R58
4.99K_1%_04
R58
4.99K_1%_04
Q3
MTN7002ZHS3
Q3
MTN7002ZHS3
G
DS
Q5
MTN7002ZHS3
Q5
MTN7002ZHS3
G
DS
R50 *0_04R50 *0_04
R91 *10K_04R91 *10K_04
C37
*22u_6.3V_X5R_08_E
C37
*22u_6.3V_X5R_08_E
R30
*39_04
R30
*39_04
R31
*100K_04
R31
*100K_04
R43 *10mil_04R43 *10mil_04
R251K_04 R251K_04
C36
*22u_6.3V_X5R_08_E
C36
*22u_6.3V_X5R_08_E
C46 *0.1u_16V_Y5V_04C46 *0.1u_16V_Y5V_04
R73 *100_04R73 *100_04
R76 10K_04R76 10K_04
R69 *100_1%_04R69 *100_1%_04
R92 *10K_04R92 *10K_04
R39 *2K_1%_04R39 *2K_1%_04
R24 *0_06R24 *0_06
R70 51_04R70 51_04
R44 130_1%_04R44 130_1%_04
R33 1K_04R33 1K_04
R37*75_04 R37*75_04
Q4
*MTN7002ZHS3
Q4
*MTN7002ZHS3
G
DS
Sheet 3 of 46
Processor 2/7