Service manual

Schematic Diagrams
Clock Generator (71-P2970-002A) B - 5
B.Schematic Diagrams
Clock Generator
Sheet 4 of 28
Clock Generator
+3V
+3V
+3V
+3V
+3V
V_CORE
+5V
+3V
Z0405
Z0403
Z0412
Z0410
Z0411
Z0421
Z0422
Z0425
Z0426
VTT_PWRGD#
Z0404
Z0406
VTT_PWRGD#
Z0419
Z0409
Z0408
Z0407
Z0417
Z0415
Z0418
Z0416
Z0413
Z0414
Z0429
Z0430
CLK100#
CLK100Z0424
Z0423
CLK100
Z0402
CLK100#
Z0401
Z0432
Z0433
Z0420
Z0427
TZ0401
TZ0402
TZ0403
TZ0404
CP36
10p
R402 1_1%
R355
49.9_1%
R381 33_1%
R603 33_1%
R391 33_1%
R382 33_1%
U22
ICS952618
6
11
17
25
33
39
45
53
54
42
50
3
10
16
24
36
55
35
29
37
44
2
12
13
14
15
18
19
20
51
56
7
30
31
32
21
22
23
26
27
49
52
47
43
40
46
38
48
41
9
28
4
8
1
5
34
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDCPU
CPU_STOP#
VDDREF
VDDPCI
VDDPCI
VDD3V66
VDDSRC
VDDA
VTT_PWRGD#
3V66_4/VCH_CLK
SRCCLKC
CPUCLKT1
REF1
PCICLK0/Reset_EN
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
FS_A
FS_B
PCICLK_FS2
SDATA
24_48MHz/SEL24_48#
48MHz_0/FS3
PD#
3V66_0/Reset#
3V66_1
3V66_2
3V66_3
PCI_STOP#
IREF
CPUCLKT2
CPUCLKC1
CPUCLKC0
CPUCLKC2
SRCCLKT
VDDCPU
CPUCLKT0
PCICLK_F2
SCLK
X1
PCICLK_FS4
REF0
X2
VDD48
CP11
10p
CP39
10p
CP9
10p
R365 33_1%
R362 33_1%
CP25
33p
R99
475_1%
CP27
10p
CP29
10p
R105
10_1%_R
CA83
0.1u_X7R
CP32
10p
CP35
10p
+
CT56
10u/10V_1206
CP22
10p
R375 1K
R384 33_1%
CP3
10p
Q33
2N3904
B
E
C
R383 33_1%
CP10
10p_R
CP37
10p
CP38
10p
R349 33_1%_R
R376 33_1%
R379 33_1%
R312
2.49K_1%
R313
2.49K_1%
R403
220
CA224
0.1u_X7R
R395 10K
R353
1K_1%
R378 33_1%
R351
1K_1%
R361
49.9_1%
R458 10K
R352
0_R
Y2
14.318MHz
12
C223
18p
R459 10K_R
C224
18p
R368
49.9_1%
L44
BK2125HM121-120 ohm-300mA_0805
R392 33_1%_R
R369 33_1%
R320 2K_1%
R350 33_1%
CA79
0.1u_X7R
R359 10K
R457
0
R356 10K
R456
0_R
CA86
0.1u_X7R
L45 BK2125HM121-120 ohm-300mA_0805
R358
49.9_1%
CT57
10u/10V_1206
R390 10K
R393 10K
R364
49.9_1%
CA77
0.1u_X7R
CA225
0.1u_X7R
R321 2K_1%
CA227
0.1u_X7R
R380
49.9_1%
R372
49.9_1%
R377
49.9_1%
CT58
10u/10V_1206
CA221
0.1u_X7R
R373 33_1%
R371 33_1%
R357 33_1%
R363 33_1%
R354 33_1%
R367 33_1%
R360 33_1%
C78
0.01u
R347 33_1%
SMBCLK[10,14,16,22]
MINI-PCLK [19]
SMBDATA[10,14,16,22]
ITPCLK# [3]
MCHCLK [6]
MCHCLK# [6]
SIOPCLK [22]
ICH-48M [14]
SIO-48M [22]
+3V [3,5,6,11,12,13,14,15,16,17,19,20,21,22,23,24,26,27,28]
V_CORE [2,3,14,22,27]
MBID1 [22]
MBID2 [22]
CPUCLK# [3]
ITPCLK [3]
CPUCLK [3]
BSEL0[6]
ICH66CLK [14]
MCH66CLK [7]
CLK100 [14]
CLK100# [14]
FSA[3]
FSB[3]
BSEL1[6]
ALC650 [24]
+5V [11,12,13,14,16,17,19,21,22,23,24,25,26,27,28]
PCLK [17]
ICH-14M [14]
DREFCLK [7]
CH7017A-CLK [11]
LANPCLK [20]
FWHPCLK [21]
ICHPCLK [15]
Iref=2.32mA
CPU
33.33
(MHz)
1
33.33
PCI
(MHz)
200.00
0
100/200
133.33
33.33
(FSB)
0
1
0
(MHz)(MHz)
SRC
100.000
FREQUENCY SETUP TABLE
AGP
66.67
ID3
ID2
ID1
ID4
1
100/200
100/200
66.67
66.67
(FS2)(FS3)(FS4) (FSA)
0
0
0
0
0
0
0
0
0
MBID1 MBID2
0
1 = HI , 0 = LOW
1
1
00
01
V1.0 V2.0
V3.0