Service manual

Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG) B - 5
B.Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
+1.5S_CPU 7,37
1.1VS_VTT_PWRGD21,41
Q13
*MTN7002ZHS3
G
DS
R162
*10K_04
3.3V
3.3V
+1.5S_C PU
U11
*74AHC 1G08GW
1
2
5
4
3
DRAMPWR GD_CPU
Q12
*2N3904
B
E C
+1.5S_C PU_PWR GD 40
3.3V
C222 *.1u_10V_X7R_04
R163
*10K_04
SY S_AGENT_PWROK
H_CPURST#
DDR3 Compensation Signals
H_PROCHOT#_D
Processor Pullups
XD P _ TD I _ M
XDP_TRST#
1.5V 10,11,31,37,40
H_PROCHOT#43
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
PROCESSOR 2/7 ( CLK,MISC,JTAG )
H_COMP2
H_COMP3
H_COMP1
H_COMP0
R107 *68_04
R128 *12.4K_1%_04
R67 *51_04
R69 *51_04
R130 10K_04
R159 1.5K_1%_04
R125 49.9_1%_04
R421 20_1%_04
R110 0_04
R153 *0_04
R440 24.9_1%_04
R419 49.9_1%_04
R418 51_04
R60 *51_04
R131 10K_04
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3 MISC
JTAG & BPM
U40B
PZ98927-3641-01F
SM_RCOMP[1]
AM1
SM_RCOMP[2]
AN1
SM_DRAMRST#
F6
SM_RCOMP[0]
AL1
BCLK#
B16
BCLK
A16
BC LK_ITP#
AT30
BCLK_ITP
AR30
PEG_CLK#
D16
PEG_CLK
E16
DPLL_REF_SSCLK#
A17
DPLL_REF_SSCLK
A18
CATERR#
AK14
COMP3
AT23
PECI
AT15
PROCH OT#
AN26
THERMTRIP#
AK15
RESET_OBS#
AP26
VCCPWRGOOD_1
AN14
VCCPWRGOOD_0
AN27
SM_DRAMPWROK
AK13
VTTPWRGOOD
AM15
RSTIN#
AL14
PM_EXT_TS#[0]
AN15
PM_EXT_TS#[1]
AP15
PRDY #
AT28
PREQ#
AP27
TCK
AN28
TMS
AP28
TRST#
AT27
TDI
AT29
TD O
AR27
TDI _M
AR29
TD O_M
AP29
DBR#
AN25
BPM#[0]
AJ22
BPM#[1]
AK22
BPM#[2]
AK24
BPM#[3]
AJ24
BPM#[4]
AJ25
BPM#[5]
AH22
BPM#[6]
AK23
BPM#[7]
AH23
COMP2
AT24
PM_SY NC
AL15
TAPPW R GOOD
AM26
COMP1
G16
COMP0
AT26
SKTOCC#
AH24
R109 68_04
R424 20_1%_04
R115 *0_04
R129 *0_04
TRACE WIDTH 10MIL, LENGTH <500MILS
R441 100_1%_04
R155
750_1%_04
R433 49.9_1%_04
R108 51_04
R68 *51_04
R439 130_1%_04
XD P _ TM S
1.1VS_VTT
1.1VS_VTT
1.1VS_VTT
BCLK_CPU_P 24
CLK_DP_P 20
CLK_DP_N 20
H_CPUPWRGD24
BUF_PLT_RST#23,28,31,32,36
PM_DRAM_PWRGD21
H_VTTPWRGD21
BCLK_CPU_N 24
H_THRMTRIP#24
CLK_EXP_N 20
CLK_EXP_P 20
1.1VS_VTT 2,6,7,19,20,21,24,25,26,39,41,42,43
H_PECI24,36
PM_EXTTS#_EC 3
TS#_DIMM0_1 10,11
DELAY_PWRGD21, 43
H_PM_SYNC21
R134
1.1K_1%_04
VDDPWRGOOD_R
R158
3K_1%_04
+1.5S_C PU
R157
*1.5K_1%_04
DRAMPWR GD_CPU
R114 *10m il_short
H_PROCHOT#_D
R156 *10m il_short
C1126
0.1u_10V_X7R_04
R416 *10m il_short
XDP_TDO_ M
H_CPURST#
Processor Compensation
Signals
H_PWRGD_XDP
PL T_R ST# _R
XDP_P REQ #
XDP_TCLK
XDP_TRST#
XDP_TMS
Connect to the Processor (V TTPWRGOOD) VT T_ 1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
H_COMP3
SY S_AGENT_PWR OK
H_COMP2
PM_EXTTS#[1]
H_COMP1
Signal from PCH to Processor
Connect to PCH (P LT_RST#)
(needs to be level translate d
from 3.3 V to 1.1 V).
CPU_DRAMRST#
SM_RCOMP_0
XD P _ TD O _ M
3.3V 3,12,13,17,19,20, 21,23,24,26,28, 29,31,32,33,34,37,39,40,41,44
XD P _ TD I _ R
SM_RCOMP_1
VDDPWRGOOD_R
SM_RCOMP_2
H_CATERR#
XD P _ P R E Q #
XD P _ TC L K
R246
*1K_04
Q32
*MTN7002ZHS3
G
D S
R241
*100K_04
R250 0_04
XDP_TDI _R
R234 *0_04
DDR3_DRAMRST#10,11
1.5V
DDR3_DRAMRST#
DRAMRST_CNTRL_PCH24
CPU_DRAMRST#
C360
*470p_50V_X7R_04
PM_EXTTS#[0]
DRAMRST_CNTRL9
H_COMP0
XDP_TDI _M
XD P _ TD O _ M
R121 0_04
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
H_CATERR#
Sheet 4 of 53
CPU 2/7
(CLK, MISC, JTAG)