Service manual

Schematic Diagrams
Clock Generator B - 3
B.Schematic Diagrams
Clock Generator
CLK_SCLK
CLK_SDATA
CLK_SCLK
3.3VS
REF_0/CPU_SEL
CPU_STOP#
REF_0/CPU_SEL
CLK_SDATA
XO U T
REF_0/CPU_SEL
XI N
PR121 2.2K_04
CLK_PWRGD
C483
1u_16V_X5R_06
C482
0.1u_16V_Y5V_04
R328
10K_04
X4 F SX5L_ 14.318 18MH z
12
L33 *H CB1608KF-121T25_32m il_short
PR120 2.2K_04
C436
33p_50V_NPO_04
C435
33p_50V_NPO_04
R322
1M_04
C491
0.1u_16V_Y5V_04
Q37
MTN7002ZHS3
G
DS
L31
*HCB1608KF-121T25_32mil_short
PR117 33_04
PR118 *4.7k_04
PR122 2.2K_04
Q38
MTN7002ZH S3
G
D S
C467
1u_16V_X5R_06
C475
0.1u_16V_Y 5V_04
U29
SLG8SP585
VDD _DOT
1
VDD _27
5
VDD _SR C
17
VDD _CPU
24
VDD _REF
29
VSS_DOT
2
XT AL _ O U T
27
XT AL _ I N
28
REF_0/CPU_SEL
30
SDA
31
SCL
32
VSS_27
8
VSS_SATA
9
VSS_SRC
12
VSS_CPU
21
VSS_REF
26
VDD_SRC_I/O
15
VDD_CPU_I/O
18
DOT_96
3
DOT_96#
4
27M
6
27M_SS
7
SRC_1/SATA
10
SRC _1#/SATA#
11
SRC_2
13
SRC_2#
14
CPU_STOP#
16
CPU_1
20
CPU_1#
19
CPU_0
23
CPU_0#
22
CKPWR GD/ PD#
25
GND
33
PR119 10K_04
Q36
MTN7002ZH S3
G
D S
C437 *10P_50V_04
3.3VS
CLK_VCC1
CLK_VCC2CLK_VC C 1
XO U T
XI N
3.3VS
3.3VS3.3VS
1.1VS_VTT
CLK_VCC2
CLK_BUF_BCLK_N 20
CLK_BUF_BCLK_P 20
CLK_BUF_DOT96_N 20
CLK_BUF_REF1420
CLK_BUF_DOT96_P 20
3.3VS
CLKEN#43
1.1VS_VTT 4, 6,7,19,20,21,24,25,26, 39,41,42,43
SMB_DATA10,11,20
SMB_CLK10,11,20
CLKGEN POWER
CLK_SATA# 20
CLK_SATA 20
CLK_PCIE_ICH# 20
CLK_PCIE_ICH 20
1(0.7V-1.5V)
0(default)
PIN_30 CPU_1CPU_0
EMI
EMI Capactior
VDD_I/O can be
ranging from
1.05V to 3.3V
0.1uF near the every power pin
0.1uF near the every power pin
9LRS3197
CLOCK GENERATOR
CPU_SEL_During CK_PEWGD Latch Pinl
SMBus
100MHz100MHz
133MHz133MHz
3.3VS 10,11,12,13,19,20,21,22,23,24,25,26,28,29,30,32,33,35,36,37,42,43,46
Sheet 2 of 53
Clock Generator