Service manual

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SiS5102 PCI Local Data Buffer
• Supports full 64-bit Pentium processor data bus.
• Provides a 64-bit interface to DRAM memory.
• Provides a 32-bit interface to PCI.
• Three integrated posted write buffers and two read buffers increase system
performance.
∗ 1 level CPU-to-Memory Posted Write Buffer (CTMPB) with 4 QuadWords
(QWs) deep.
∗ 4 level CPU-to-PCI Posted Write Buffer (CTPPB) with 4 DoubleWords
(DWs) deep.
∗ 1 level PCI-to-Memory Posted Write Buffer (PTMPB) with 1 QW deep.
∗ 1 level Memory-to-CPU Read Buffer (CRMB) with 1 QW deep.
∗
1 level Memory-to-PCI Read Buffer (PRMB) with 1 QW deep.
• Near Zero wait state performance on CPU-to-Memory and CPU-to-PCI writes.
• Operates synchronously to the 66.7 MHz CPU aand 33.3 MHz PCI clocks.
• Provides parity generation for memory writes.
• 208-pin PQFP.
• 0.6um CMOS technology.