Service manual

85
SiS5101 PCI Cache Memory Controller
• Supports Pentium, K5 and M1 processors.
• Integrated Second Level (L2) Cache Controller.
∗ Write through and write back cache modes.
∗ 8 bits or 7 bits tag with Direct Mapped Organization.
∗ Supports standard and burst SRAMs.
∗ Supports SRAM standard mode.
∗ Supports 64 Kbytes to 2 Mbytes cache sizes.
∗ Cache read/write cycle of 3-2-2-2 or 4-2-2-2 using standard SRAMs at
66MHz.
∗ Cache read/write cycle of 3-1-1-1 using burst SRAMs at 66MHz.
•
Integrated DRAM controller.
∗ Supports 4 banks of SIMMs up to 256 Mbytes of cacheable main memory.
∗ Supports “table-free” DRAM configuration.
∗ Concurrent write back.
∗ CAS#-before-RAS# transparent DRAM refresh.
∗ Supports 256K/512K/1M/2M/4M/8M/16MxN 70ns Fast Page Mode and
EDO DRAM.
∗ The fastest burst cycle speed for FP and EDO are 6-3-3-3 and 6-2-2-2
respectively.
∗
Programmable CAS# driving current.
∗ Programmable DRAM speed.
∗ Supports slow refresh.
• Two programmable non-cacheable regions.
• Supports synchronous and asynchronous PCI clock.
• Supports SMI/SMM mode.
• Supports CPU stop clock.
• Provides high performance PCI arbiter.
∗
Supports four PCI masters.
∗ Supports rotating priority mechanism.
∗ Hidden arbitration scheme minimizes arbitration overhead.
• Integrated PCI bridge.
∗ Translates the CPU cycles into the PCI bus cycles.
∗ Provides CPU-to-PCI read assembly and write disassembly mechanism.
∗ Translates sequential CPU-to-PCI memory write cycles into PCI burst
cycles.
∗ PCI burst write in the pace of X-2-2-2…
∗ PCI burst read L2 cache in X-2-2-2…
∗ PCI burst read DRAM in X-3-2-3-2…
∗ Cache snoop filters ensure data coherency and minimizes snoop
frequency.
∗ meet PCI specification buffer strength.
• Supports Leakage control.
• Supports suspend to Memory.
• 208-pin PQFP/TQFP package.
•
0.6um CMOS technology.