User manual

I570 Motherboard User Manual
46
7.5 Advanced Chipset Feature
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable [By SPD]
Item Help
X CAS Latency Time 2.5
Menu Level ►
X DRAM RAS# to CAS# Delay 3
X DRAM RAS# Precharge 3
X Precharge delay (tRAS) 8
MGM Core Frequency [Auto Max 266MHz]
System BIOS Cacheable [Enabled]
Video BIOS Cacheable [Disabled]
Memory Hole At 15-16M [Disabled]
Delayed Transaction
Delay Prior to Thermal
AGP Apertrue Size
↑↓→←:Move Enter:Select +/-/PU/PD:Value F10:Save Esc:Exit F1:Genenal Help
F5: Previous Values F6: Fail -Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The
default is By SPD.
CAS Latency Time
You can configure CAS latency time in HCLKs as 2 or 2.5 or 3. The system
board designer should set the values in this field, depending on the DRAM
installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe)
and CAS (Column Address Strobe) si gnals. This delay occurs when the
SDRAM is written to, read from or refreshed. Reducing the delay improves the
performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its
charge before the SDR AM refreshes. The default setting for the Active to
Precharge Delay is 4.