Data Sheet

Seite 5/13
7
RTS/CLK
UART ready to send / SPI clock
output/input
8
CTS/CS
UART clear to send / SPI chip select
input
9
TXD/MISO
UART output / SPI Master input
output
10
RXD/MOSI
UART input / SPI Master output
input
Table 1 Pin description
6.3.1 POWER SUPPLY
Decoupling capacitors between VDD and GND are not mandatory.
6.3.2 HOST INTERFACE
Communication between BLE module and host can be established through UART or SPI by using
TXD/MISO, RXD/MOSI, CTS/CS and RTS/CLK. The communication interface is disabled through
COM_DISABLE pin.
6.3.3 GPIO
GPIO1 can be used for any purpose and has analogue capabilities.
6.3.4 JTAG/SWD
SWDIO and SWCLK are required for programming and debugging and must be accessible on the BLE
Module. Image 2 shows the standard 10 pin cortex debug connector.
Image 2 Programming interface