User`s guide

Rev. 1.10 96 November 14, 2014 Rev. 1.10 97 November 14, 2014
HT66FW2230
Wireless Charger A/D Flash 8-Bit MCU
intransmitmodeorreceivemode.IftheIICSRWagishigh,themasterisrequesting
toreaddatafromthebus,sotheslavedeviceshouldbeintransmitmode.Whenthe
IICSRWagiszero,themasterwillwritedatatothebus,thereforetheslavedevice
shouldbeinreceivemodetoreadthisdata.
Bit1 IICRNIC:I
2
CrunningusingInternalClockControl
0:I
2
Crunningusinginternalclock
1:I
2
CrunningnotusingInternalClock
TheI
2
Cmodulecanrunwithoutusinginternalclock,andgenerateaninterruptifthe
I
2
Cinterruptisenabled,whichcanbeusedinSLEEPMode,IDLE(SLOW)Mode.
Bit0 IICRXAK:I
2
CBusReceiveacknowledgeag
0:Slavereceiveacknowledgeag
1:Slavedonotreceiveacknowledgeag
TheIICRXAKagisthereceiveracknowledgeag.WhentheIICRXAKagis“0”,
itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsof
datahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslave
devicecheckstheIICRXAKagtodetermineifthemasterreceiverwishestoreceive
thenextbyte.Theslavetransmitterwillthereforecontinuesendingoutdatauntilthe
IICRXAKagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAline
toallowthemastertosendaSTOPsignaltoreleasetheI
2
CBus.
TheIICDregisterisusedtostorethedatabeingtransmittedandreceived.Beforethedevicewrites
datatotheI
2
Cbus,theactualdatatobetransmittedmustbeplacedintheIICDregister.Afterthe
dataisreceivedfromtheI
2
Cbus,thedevicecanreaditfromtheIICDregister.Anytransmissionor
receptionofdatafromtheI
2
CbusmustbemadeviatheIICDregister.
IICD Register
Bit 7 6 5 4 3 2 1 0
Name IICDD7 IICDD6 IICDD5 IICDD4 IICDD3 IICDD2 IICDD1 IICDD0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x x
“x” unknown
Bit7~0 IICDD7~IICDD0:I
2
CDataBufferbit7~bit0
IICA Register
Bit 7 6 5 4 3 2 1 0
Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 —
R/W R/W R/W R/W R/W R/W R/W R/W —
POR x x x x x x x —
“x” unknown
Bit7~1 IICA6~IICA0:I
2
Cslaveaddress
IICA6~IICA0istheI
2
Cslaveaddressbit6~bit0.
TheIICAregisteristhelocationwherethe7-bitslaveaddressoftheslavedevice
isstored.Bits7~1oftheIICAregisterdenethedeviceslaveaddress.Bit0isnot
dened.
Whenamasterdevice,whichisconnectedtotheI
2
Cbus,sendsoutanaddress,which
matchestheslaveaddressintheIICAregister,theslavedevicewillbeselected.
Bit0 Unimplemented,readas"0"