User`s guide

Rev. 1.10 86 November 14, 2014 Rev. 1.10 87 November 14, 2014
HT66FW2230
Wireless Charger A/D Flash 8-Bit MCU
Bit4~3 VREFS1~VREF0:SelectADCreferencevoltage
00:InternalADCpower
01:ExternalVREFpin
1x:InternalV
REF

ThesebitsareusedtoselectthereferencevoltagefortheA/Dconverter.Ifthesebits
are“01”thentheA/DconverterreferencevoltageissuppliedontheexternalVREF
pin.Ifthesebitsaresetto“1x”thentheA/Dconverterreferencevoltageissupplied
ontheinternalVREF.Ifthesebitsaresetto“00”thentheinternalreferenceisused
whichistakenfromthepowersupplypinAVDD.
Bit2~0 ADCK2 ~ ADCK0:SelectADCclocksource
000:f
SYS
001:f
SYS
/2
010:f
SYS
/4
011:f
SYS
/8
100:f
SYS
/16
101:f
SYS
/32
110:f
SYS
/64
111:f
SUB

ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.
A/D Operation
TheSTARTbitintheADCR0registerisusedtostartandresettheA/Dconverter.Whenthe
microcontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversion
cyclewillbeinitiated.WhentheSTARTbitisbroughtfromlowtohighbutnotlowagain,the
EOCBbitintheADCR0registerwillbesethighandtheanalogtodigitalconverterwillbereset.
ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigital
converter.
TheEOCBbitintheADCR0registerisusedtoindicatewhentheanalogtodigitalconversion
processiscomplete.Thisbitwillbeautomaticallysetto“0”bythemicrocontrolleraftera
conversioncyclehasended.Inaddition,thecorrespondingA/Dinterruptrequestagwillbeset
intheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterrupt
signalwillbegenerated.ThisA/Dinternalinterruptsignalwilldirecttheprogramflowtothe
associatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,
themicrocontrollercanbeusedtopolltheEOCBbitintheADCR0registertocheckwhetherithas
beenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.
TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockf
SYS
,canbechosen
tobeeitherf
SYS
orasubdividedversionoff
SYS
.Thedivisionratiovalueisdeterminedbythe
ADCK2~ADCK0bitsintheADCR1register.
AlthoughtheA/Dclocksourceisdeterminedbythesystemclockf
SYS
,andbybitsADCK2~ADCK0,
therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.Asthe
recommendedrangeofpermissibleA/Dclockperiod,t
ADCK
,isfrom0.5μsto10μs,caremustbe
takenforsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequencyof
5MHz,theADCK2~ADCK0bitsshouldnotbesetto000B,001Bor110B.DoingsowillgiveA/
DclockperiodsthatarelessthantheminimumA/DclockperiodorgreaterthanthemaximumA/D
clockperiodwhichmayresultininaccurateA/Dconversionvalues.
Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,
dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecied
minimumA/DClockPeriod.