User`s guide
Rev. 1.10 72 November 14, 2014 Rev. 1.10 73 November 14, 2014
HT66FW2230
Wireless Charger A/D Flash 8-Bit MCU
Standard Type TM Register Description
OveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregister
pairexiststostoretheinternalcounter10-bitvalue,whilearead/writeregisterpairexiststostore
theinternal10-bitCCRAvalue.Theremainingtworegistersarecontrolregisterswhichsetupthe
differentoperatingandcontrolmodesaswellasthethreeCCRPbits.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TM0C0 T0PAU
T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0PR1 T0PR0
TM0C1 T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR
TM0DL D7 D6 D5
D4 D3 D2 D1 D0
TM0DH — — — — — — D9 D8
TM0AL D7 D6 D5
D4 D3 D2 D1 D0
TM0AH — — — — — — D9 D8
10-bit Standard TM Register List
TM0C0 Register
Bit 7 6 5 4 3 2 1 0
Name T0PAU T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0PR1 T0PR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 T0PAU:TM0CounterPauseControl
0:Run
1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebittozerorestores
normalcounteroperation.WheninaPauseconditiontheTMwillremainpoweredup
andcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbit
changesfromlowtohighandresumecountingfromthisvaluewhenthebitchanges
toalowvalueagain.
Bit6~4 T0CK2~T0CK0:SelectTM0Counterclock
000:f
SYS
/4
001:f
SYS
010:f
H
/16
011:f
H
/64
100:f
SUB
101:f
SUB
110:TCK0risingedgeclock
111:TCK0fallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheTM0.Theexternalpinclock
sourcecanbechosentobeactiveontherisingorfallingedge.Theclocksourcef
SYS
is
thesystemclock,whilef
H
istheHXToscillatorandf
SUB
isinternalclock,thedetails
ofwhichcanbefoundintheoscillatorsection.
Bit3 T0ON:TM0CounterOn/OffControl
0:Off
1:On
Thisbitcontrolstheoverallon/offfunctionoftheTM0.Settingthebithighenables
thecountertorun,clearingthebitdisablestheTM0.Clearingthisbittozerowill
stopthecounterfromcountingandturnofftheTM0whichwillreduceitspower
consumption.Whenthebitchangesstatefromlowtohightheinternalcountervalue
willberesettozero,howeverwhenthebitchangesfromhightolow,theinternal
counterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheTM0isin
theCompareMatchOutputModethentheTM0outputpinwillberesettoitsinitial
condition,asspeciedbytheT0OCbit,whentheT0ONbitchangesfromlowtohigh.