User`s guide

Rev. 1.10 102 November 14, 2014 Rev. 1.10 103 November 14, 2014
HT66FW2230
Wireless Charger A/D Flash 8-Bit MCU
PLL Clock Generator
ThedeviceprovidesaclockgeneratoroutputwhichcanbeusedasaPWMdriversignal.The
accompanyingblockdiagramshowstheoverallinternalstructureoftheclockgenerator,together
withitsassociatedregisters.
f
HXT
frequency output =
100K~220kHz
(duty 50%, step=100Hz)
/2
Mux
CKIS=
0: f
HXT
/2
1: f
HXT
Mux
frequency output=
1MHz clock generator
Duty=50%
Clock generator
output
CKOS=
0: 100K~220kHz
1: 1MHz
10MHz
Clock
generator 1
Clock
generator 2
Clock Generator Block Diagram
220pF
4.7nF
132K
PLLCOM
PLLCOM Pin External Circuit
Clock Generator Operation
Thegeneratorclock,cancomefromeitherf
HXT
orf
HXT
/2,andisselectedusingtheCKISbitinthe
CKGENregister.ThePLLENandF1MENbitsintheCKGENregisterareusedtocontrolclock
generator1andclockgenerator2respectively.Theoutputfrequencyoftheclockgenerator1is
withinarangeof100K~220K(step=0.1KHz)whiletheclockgenerator2outputfrequencyis1MHz.
ClockGeneratoroutputcancomefromgenerator1outputorgenerator2outputwhichisselected
byCKOSbitintheCKGENregister.Theoutputfrequencyoftheclockgenerator1isselectedby
PLLFLandPLLFHregisters.
TheclockoutputcanbeusedasPWMdriversignal.ThePWM0EN~PWM2ENbitsinthePWMC
register,determinewhetherthePWMoutputfunctionisenabled.Theaccompanyingwaveform
diagramshowstherelationshipbetweentheclockgeneratoroutputandPWMsignalfordifferent
outputpins.
Clock generator output
PC0/PWM0
PC1/PWM0B
PC2/PWM1
PC3/PWM2
OC (Over current)
Clock Generator Output Driver Block Diagram