Specifications

ESS Technology, Inc. SAM0025A-062397 95
ES1879 DATA SHEET
TIMING CHARACTERISTICS
PRELIMINARY
TIMING CHARACTERISTICS
a. In Compatibility mode DMA, the DMA request is reset by the acknowledge signal going low. In Extended mode DMA, the DMA request
is reset when the acknowledge signal is low AND the correct command signal is low – either IORB (for DMA read from I/O device) or
IOWB (for DMA write to I/O device). For Extended mode DMA, the time t
10
is relative to the later of the falling edge of the acknowledge
signal or the command signal.
Symbol Parameter Min Typ Max Unit
t
1
Reset pulse width 300 ns
t
2
IORB, IOWB pulse width 100 ns
t
3
IORB, IOWB address setup time 10 ns
t
4
Read data access time 70 ns
t
5
Read data hold time 10 ns
t
6
Write data setup time 5 ns
t
7
Write data hold time 10 ns
t
8
DMA request to AEN high 0 ns
t
9
DMA request to DMA ACK low 10 ns
t
10
DMA ACK to request release
a
30 ns
t
11
DMA ACK high to AEN low 0 ns
t
12
DMA ACK to IOWB, IORB low 0 ns
t
13
IOWB, IORB to DMA ACK release 20 ns
t
14
Crystal frequency, XI/XO 14.318 MHz
t
15
FS, DS setup time to DCLK falling edge 15 ns
t
16
FS, DR hold time from DCLK falling edge 10 ns
t
17
DX delay time from DCLK rising edge 20 ns
t
18
DX hold time from DCLK rising edge 10 ns
t
19
FS pulse width 60 500 ns
t
20
DCLK clock frequency 2.048 MHz
t
21
IISCLK delay 2 ns
t
22
IISCLK setup 32 ns
t
23
Bit clock low 22 ns
t
24
Bit clock high 22 ns
t
25
Data setup time 32 ns
t
26
Data hold time 2 ns