Specifications

ESS Technology, Inc. SAM0025A-062397 83
ES1879 DATA SHEET
REGISTERS
PRELIMINARY
Audio 1 Transfer Type (B9h, R/W)
Bit Definitions:
Left Channel ADC Offset Adjust (BAh, R/W)
This register is reset to zero by hardware reset and is
unaffected by software reset.
Bit Definitions:
Right Channel ADC Offset Adjust (BBh, R/W)
This register is reset to zero by hardware reset and is
unaffected by software reset.
Bit Definitions:
Bits 4 (sign) and 3:0 (adjust magnitude) of the ADC Offset
Adjust register cause a constant value to be added to the
ADC converter output, as shown in the following:
Formula:
bit 4 = 0: offset = 64 * bits[3:0]
bit 4 = 1: offset = -64 * (bits[3:0] +1)
To calculate the offset adjust code, first measure the ADC
offset for both right and left channels before adjustment by
following these steps:
1. Program Extended mode registers BAh and BBh
bits 4:0 to be zero (no digital offset).
2. Select a zero-amplitude (or low amplitude)
recording source.
3. Set the recording volume to minimum by setting
Extended mode register B4h to zero.
4. Make a stereo 16-bit two’s complement recording
at 11 kHz sample rate of 2048 stereo samples
(2048 stereo samples = 4096 words = 8192 bytes,
which is about 190 msec).
5. Use the last 1024 stereo samples to calculate a
long-term average for both left and right channels.
6. With this average DC offset, calculate the best
digital offset to bring the sum closest to zero, using
the codes and offsets listed in the table above.
0 DMA transfer type select
76 5432 1 0
Bits Name Description
7:2 – Reserved. Always write 0.
1:0 DMA
transfer
type select
Selects the DMA transfer type for the first
DMA:
bit 1 bit 0 Transfer Type Bytes/DMA Request
0 0 Single –
0 1 Demand 2
1 0 Demand 4
1 1 Reserved –
0
Disable time delay on
analog wake up
Sign Adjust magnitude
7 6 5 43210
Bits Name Description
7:6 – Reserved. Always write 0.
5 Disable time
delay on
analog
wake up
Normally, the AOUT_L and AOUT_R pins
are muted for 100 msec ± 20 msec after
hardware reset or after the analog sub-
systems wake from power-down. Set high to
disable delay.
This bit is cleared by hardware reset.
4:0 Sign/Adjust
magnitude
See the explanation for bits 4:0 following
register BBh.
0 Sign Adjust magnitude
76543210
Bits Name Description
7:5 0 Reserved. Always write 0.
4:0 Sign/Adjust
magnitude
See the following explanation for bits 4:0.
Code Offset Code Offset
00h 0 10h -64
01h +64 11h -128
02h +128 12h -192
03h +192 13h -256
04h +256 14h -320
05h +320 15h -384
06h +384 16h -448
07h +448 17h -512
08h +512 18h -576
09h +576 19h -640
0Ah +640 1Ah -704
0Bh +704 1Bh -768
0Ch +768 1Ch -832
0Dh +832 1Dh -896
0Eh +896 1Eh -960
0Fh +960 1Fh -1024