Specifications

80 SAM0025A-062397 ESS Technology, Inc.
ES1879 DATA SHEET
REGISTERS
PRELIMINARY
Audio 1 Filter Clock Divider (A2h, R/W)
This register controls the low-pass frequency of the
switch-capacitor filters inside the ES1879. Generally, the
filter roll-off should be positioned at 80%-90% of the
Sample_Rate/2 frequency. The ratio of the roll-off
frequency to the filter clock frequency is 1:82. In other
words, first determine the desired roll-off frequency by
taking 80% of the Sample_Rate divided by 2, then multiply
by 82 to find the desired filter clock frequency. Use the
formula below to determine the closest divider:
Filter_Clock_Frequency = 7.16 MHz / (256-Filter_Divider_Register)
Audio 1 Transfer Count Reload (A4h, R/W)
On reset, this register assumes the value of 00h.
Audio 1 Transfer Count Reload (A5h, R/W)
On reset, this register assumes the value of F8h.
The FIFO control logic of the ES1879 has a 16-bit counter
for controlling transfers to and from the FIFO. These
registers are the reload value for that counter, which is the
value that gets copied into the counter after each overflow
(plus at the beginning of the initial DMA transfer). The
counter is incremented after each byte is successfully
transferred by DMA. Since the counter counts up towards
FFFFh and then overflows, the reload value is in two’s
complement form.
For Auto-Initialize mode DMA, the counter is used to
generate interrupt requests to the system processor. In
this mode, the ES1879 allows continuous DMA. In a
typical application, the counter is programmed to be one-
half of the DMA buffer maintained by the system
processor. In this application, an interrupt is generated
whenever DMA switches from one half of the circular
buffer to the other.
For Normal mode DMA, DMA requests are halted at the
time that the counter overflows, until a new DMA transfer
is commanded by the system processor. An interrupt
request is generated to the system processor if bit 6 of
register B1h is set high.
Analog Control (A8h, R/W)
When programming the FIFO for DMA playback, modify
only bits 1:0. When programming the FIFO for DMA
record, modify only bits 3, 1, and 0. Read this register first
to preserve the remaining bits.
Bit Definitions:
Filter clock divider
76543210
DMA transfer count reload – low byte
7 6543210
DMA transfer count reload – high byte
76543210
0001
Record monitor
enable
0
Stereo/mono
select
7654 3 210
Bits Name Description
7:5 – Reserved. Always write 0.
4 – Reserved. Always write 1.
3 Record
monitor
enable
1 = Enable record monitor.
0 = Disable record monitor.
2 – Reserved. Always write 0.
1:0 Stereo/
mono
select
Select operation mode of first DMA converters.
bit 1
bit 0 Mode
0 0 Reserved.
0 1 Stereo.
1 0 Mono.
1 1 Reserved.