Specifications

76 SAM0025A-062397 ESS Technology, Inc.
ES1879 DATA SHEET
REGISTERS
PRELIMINARY
Audio 2 Filter Clock Divider (72h, R/W)
This register controls the low-pass frequency of the
switch-capacitor filters inside the ES1879. Generally, the
filter roll-off should be positioned at 80% - 90% of the
Sample_Rate/2 frequency. The ratio of the roll-off
frequency to the filter clock frequency is 1:82. In other
words, first determine the desired roll-off frequency by
taking 80% of the Sample_Rate divided by 2, then multiply
by 82 to find the desired Filter Clock frequency. Use the
formula below to determine the closest divider:
Filter_Clock_Frequency = 7.16 MHz / (256-Filter_Divider_Register)
Audio 2 Transfer Count Reload (74h, R/W)
NOTE:
When suspend/resume bit is set, reading this
register returns the current counter contents.
Audio 2 Transfer Count Reload (76h, R/W)
NOTE:
When suspend/resume bit is set, reading this
register returns the current counter contents.
Audio 2 Control 1 (78h, R/W)
This register is reset to zero by hardware or software reset
via bit 0 of port Audio_Base+6h.
Bits Definitions:
Filter clock divider
76543210
2’s complement transfer count – low byte
76543210
2’s complement transfer count – high byte
76543210
DMA
transfer
type
0
Auto-Initialize
enable
00
Enable
transfer
into
FIFO
Enable
transfer
to DAC
76 5 4 3 2 1 0
Bits Name Description
7:6 DMA
transfer
type
Selects single or demand transfer for the
second audio channel:
bit 7 bit 6 transfer type bytes/DMA request
0 0 single 1
0 1 demand 2
1 0 demand 4
1 1 demand 8
5 – Reserved. Always write 0.
4 Auto-Ini-
tialize
enable
1 = Auto-Initialize mode. After the transfer
counter rolls over to 0, it is automatically
reloaded and DMA continues. The second
channel interrupt flag is set high.
0 = Normal mode. After the transfer counter
rolls over to 0, it is reloaded but DMA stops. Bit
1 of this register is cleared. The second chan-
nel interrupt flag is set high.
3:2 – Reserved. Always write 0.
1 Enable
transfer
into FIFO
1 = Enable DMA transfer into Audio 2 FIFO (32
words deep).
0 = Disable DMA transfer into FIFO. This
causes the DMA counter to be reloaded from
the reload register.
This bit is cleared automatically at the comple-
tion of a non auto-initialize transfer.
0 Enable
transfer
to DAC
1 = Enable transfer from FIFO to Audio 2 DAC
(or in special cases from the FIFO to either the
DSP serial port or to be mixed with the FM syn-
thesizer output).
0 = Disable transfer from FIFO to DAC. DAC
receives code 0 and FIFO is flushed.