Specifications

68 SAM0025A-062397 ESS Technology, Inc.
ES1879 DATA SHEET
REGISTERS
PRELIMINARY
Serial Mode Miscellaneous Control (48h, R/W)
Bits Definitions:
FS Rate Control (4Ah, R/W)
This register is used in a test mode enabled by bit 2 of
mixer register 48h.
Bits Definitions:
Serial
enable
Data
format
Serial
reset
ES689/
ES69x
interface
enable
Active
low sync
DSP
test
mode
0
Telegaming
mode enable
765 4 3 21 0
Bits Name Description
7Serial
enable
1 = Enable DSP serial port. This signal is syn-
chronized with DCLK input rising edge. If
DCLK is not running, enabling Serial enable
has no effect.
0 = Disable DSP serial port.
6Data
format
1 = Data format is 2's complement (signed).
0 = Data format is unsigned (offset binary).
5Serial
reset
1 = Reset Serial register left/right toggle flags.
0 = Release reset.
4 ES689/
ES69x
interface
enable
1 = Enable ES689/ES69x serial interface to
use the music DAC. MCLK must also go high
at least once every 20 µsecs or the DAC will
revert to FM. The mixer volume for the music
DAC is controller by mixer register 36h.
0 = Disable ES689/ES69x serial interface.
3Active
low sync
1 = Active-low frame sync pulse.
0 = Active-high frame sync pulse.
2 DSP test
mode
1 = Test mode: FS and DCLK become outputs.
DCLK is 1.5876 MHz. FS is an active-high
frame sync at a rate determined by mixer reg-
ister 4Ah.
0 = Disable DSP test mode.
1 – Reserved. Always write 0.
0 Telegam-
ing mode
enable
1 = Enables telegaming mode. In serial mode,
connect first channel DMA (otherwise known
as game-compatible DMA) to the system DAC.
This allows game-compatible audio to be
heard when in serial mode. The system DAC
gets its filter clock and volume control from the
first channel.
0 = In serial mode, the first channel DMA is not
played. The second channel is connected to
the system DAC.
0 2’s complement filter divider
76543210
Bits Name Description
7 – Reserved. Always write 0.
6:0 2’s com-
plement
filter
divider
These bits are a 2's complement (signed)
value that divides DCLK. DCLK is a clock out-
put of 1.5876 MHz. FS is an active-high frame
sync output at a rate determined by bits 6:0 of
this register.
For example, if this register is programmed
with the value 5Ch (-36 decimal), then the
frame rate is 44.1 KHz.