Specifications

58 SAM0025A-062397 ESS Technology, Inc.
ES1879 DATA SHEET
PROGRAMMING THE ES1879
PRELIMINARY
6. Program transfer type: register 78h:
Register 78h: Set bit 4 high for Auto-Initialize DMA
mode.
Bits 7:6 00: Single transfer DMA.
01: Demand transfer DMA:
2 bytes per DMA request.
10: Demand transfer DMA:
4 bytes per DMA request.
11: Demand transfer DMA:
8 bytes per DMA request.
7. Clocks and counters: registers 70h, 72h, 74h, and 76h:
Set the sample rate the same as in A1h. Set the
Transfer Count Reload to 64 bytes.
Register 70h: Audio 2 Sample Rate Generator.
Register 72h: Audio 2 Filter Clock Divider.
Registers 74h/76h: Audio 2 Transfer Count Reload
register (low/high byte, two's complement).
NOTE:
Registers 70h and 72h are slaved to registers A1h
and A2h unless Asynchronous mode is enabled (set bit 1
of register 71h).
8. Initialize and configure DAC: register 7Ah:
Register 7Ah:
Bit 2: Set high for signed, low for unsigned.
Bit 1: Set high for stereo data, low for mono.
Bit 0: Set high for 16-bit samples, low for 8-bit.
9. Set DMA and IRQ control registers B1h, B2h and 7Ah:
Register B1h: Interrupt Configuration register.
Make sure bit 6 is high. Clear bits 7 and 5.
Register B2h: DRQ Configuration register.
Verify that bit 6 is high. Clear bits 7 and 5.
Register 7Ah: Audio 2 Control 2 register.
Bit 6 enables the audio 2 interrupt request.
10.Configure system interrupt controller and DMA
controller.
11.Set bit 0 of register 78h. Since the playback FIFO is
presumably empty, the value zero is transferred to the
playback DAC at each sample clock. A click or pop
may be heard when full-duplex is enabled. To prevent
this, use command D1h to enable the Audio 1 DAC
input to the mixer after an approximate delay of 25
milliseconds.
12.Enable playback DMA by setting bit 1 of register 78h.
After 64 bytes are transferred, bit 7 of 7Ah should go
high. Poll this bit with a suitable time-out of 10
milliseconds.
13.After bit 7 of register 7Ah goes high, enable recording
by setting bit 7 of register B7h and bit 0 of register B8h.
14.As usual, discard the first 50 to 100 milliseconds of
recorded data until analog circuits have settled. Set the
audio 2 playback volume, register 7Ch.
15.During DMA:
For Auto-Initialize mode DMA transfers, read
Audio_Base+Eh to clear the interrupt request. Do not
send any other commands to the ES1879 at interrupt
time.
For Normal mode, initialize the system DMA controller
with the address and count of the next block to transfer.
Update the ES1879 Transfer Count registers if the
count is changed. To start the next transfer in the
playback channel (Audio 2), clear bits 1:0 of register
78h, then set the bits high again. To start the next
transfer in the record channel (Audio 1), clear bit 0 of
register B8h, then set it high again
To stop a DMA transaction in progress, clear bit 0 of
register B8h. To stop a DMA transaction in the
playback channel (Audio 2) after the current auto-
initialize block is finished, clear bit 4 of register 78h,
wait for the interrupt, and then clear bits 1:0 of register
78h. To stop a DMA transaction in the record channel
(Audio 1) after the current auto-initialize block is
finished, clear bit 2 of register B8h, wait for the
interrupt, and then clear bit 0 of register B8h.
16.After DMA is finished:
Restore the system interrupt controller and DMA
controller to their idle state. Monitor the FIFO Empty
status flag in port Audio_Base+Ch to be sure data
transfer is completed. A delay of 25 milliseconds is
required to let the filter outputs settle to DC levels, then
disable the Audio 2 DAC input to the mixer.
17.To conclude:
Issue another software reset to the ES1879 to initialize
the appropriate registers.