Specifications

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ESS Technology, Inc. SAM0025A-062397 57

ES1879 DATA SHEET

PROGRAMMING THE ES1879

PRELIMINARY

To stop a DMA transaction in progress, clear bit 0 of

current auto-initialize block is finished, clear bit 4 of

1:0 of register 78h.

11.After DMA is finished:

Restore the system interrupt controller and DMA

controller to their idle state. Monitor the FIFO Empty

status flag in port Audio_Base+Ch to be sure data

transfer is completed. A delay of 25 milliseconds is

required to let the filter outputs settle to DC levels, then

disable the Audio 2 DAC input to the mixer.

12.To conclude:

Issue another software reset to the ES1879 to initialize

the appropriate registers.

Full-Duplex DMA Mode (No DSP Serial Port)

The ES1879 supports stereo full-duplex DMA. In full-

duplex (FD) mode, a second audio channel has been

added to the ES1879. The second audio channel is

programmed through mixer registers.

Program the first audio channel as in “Extended Mode

Audio 1 ADC Operation” on page 54. Mixer registers A1h

and A2h can define the sample rate and filter frequency for

both record and playback. In other words, the record and

playback are at the same sample rate (synchronous). The

rate for playback can be set independently when bit 1 of

mixer register 71h is set high. This is Asynchronous mode.

Set the sample rate and filter frequency with mixer

registers 70h and 72h. When bit 1 of mixer register 71h is

low, the default state, the converters are in Synchronous

mode.

Program the second audio channel second. Mixer

registers 74h and 76h are set to the two's complement

DMA transfer count. The second audio channel supports

both Auto-Initialize DMA and Normal DMA modes. The

playback buffer in system memory does not have to be the

same size as the record buffer. When the DMA transfer

count rolls over to zero, it can generate an interrupt that is

independent of the interrupt generated by the first audio

channel.

If the record and playback buffers are the same size, then

a single interrupt can be used. Program the DMA Transfer

Count Reload registers (A4h, A5h, 74h, and 76h) with the

same value for both channels. Enable the second audio

channel before enabling the record channel. For example,

assume there are two half-buffers in a circular buffer.

When the record channel completes filling the first half, it

generates an interrupt. To ensure that the playback

channel is not accessing the first half at the time of the

interrupt, start the playback channel first. It has a 32-word

FIFO that fills quickly through DMA.

The recommended method is as follows:

Program both DMA controllers for Auto-Initialize DMA

within separate circular buffers of the same size, N.

To exit full-duplex mode, clear bits 0 and 1 of mixer register

78h.

1. Reset:

Write 3h to port Audio_Base+6h, instead of 1h as in

Compatibility mode. Bit 1 high specifically clears the

FIFO. The remainder of the software reset is identical

to Compatibility mode. Reset disables the Audio 1 DAC

input to the mixer. This masks any pops created during

the setup of the DMA transfer.

2. After the reset, send command C6h to enable

Extended mode commands.

3. Program direction and type: registers B8h, A8h, and

B9h:

mode. Leave bit 3 low to program the CODEC for the

DAC direction.

bits and modify only bits 3, 1, and 0:

Bits 1:0 10: Mono

01: Stereo

Bit 3 0: Disable Record Monitor for now.

Bits 1:0 00: Single transfer DMA.

01: Demand transfer DMA:

2 bytes per DMA request.

10: Demand transfer DMA:

4 bytes per DMA request.

4. Clocks and counters: registers A1h, A2h, A4h, and

A5h:

Registers A4h/A5h: Audio 1 Transfer Count Reload

5. Initialize and configure DAC: registers B6h and B7h:

unsigned data. This also initializes the CODEC for

DAC transfer.

Table 18, “Command Sequences for DMA Playback”

on page 53.