Specifications

56 SAM0025A-062397 ESS Technology, Inc.
ES1879 DATA SHEET
PROGRAMMING THE ES1879
PRELIMINARY
NOTE:
The ES1879 is designed for I/O block transfer up
to an ISA bus speed of 8.33 MHz.
Programmed I/O DAC Operation
Programmed I/O DAC operation is done just as explained
under “Extended Mode Audio 1 DAC Operation” on
page 53 with the following exceptions:

In step 3, programming register B9h is
unnecessary.

In step 6, leave bits 7:5 of register B2h low. Set bit
5 of register B1h high to enable an interrupt on FIFO
half-empty transitions. Keep bit 6 of register B1h
low.

In step 8, in addition to setting bit 0 of register B8h
high, send the REP OUTSB command.
Programmed I/O ADC Operation
Programmed I/O ADC operation is done just as explained
under “Extended Mode Audio 1 ADC Operation” on
page 54 with the following exceptions:

In step 5, programming register B9h is
unnecessary.

In step 9, leave bits 7:5 of register B2h low. Set bit
5 of register B1h high to enable an interrupt on FIFO
half-empty transitions. Keep bit 6 of register B1h
low.

In step 11, in addition to setting bit 0 of register B8h
high, send the REP OUTSB command.
Second Audio Channel DAC Operation
Follow the steps below to program the second audio
channel for DAC operation.
1. Reset:
Write 3h to port Audio_Base+6h, instead of 1h as in
Compatibility mode. Bit 1 high specifically clears the
FIFO. The remainder of the software reset is identical
to Compatibility mode. On reset, the playback mixer
volume for the second audio channel is set to zero,
register 7Ch. This masks any pops that might occur
during the setup process.
2. Send command C6h to enable Extended mode
commands.
3. Program transfer type: register 78h:
Register 78h: Set bit 4 low for Normal DMA mode, high
for Auto-Initialize DMA mode.
Bits 7:6 00: Single transfer DMA.
01: Demand transfer DMA:
2 bytes per DMA request.
10: Demand transfer DMA:
4 bytes per DMA request.
11: Demand transfer DMA:
8 bytes per DMA request.
4. Clocks and counters: registers 70h, 72h, 74h, and 76h:
Register 70h: Audio 2 Sample Rate Generator.
Register 72h: Audio 2 Filter Clock Divider.
Registers 74h/76h: Audio 2 Transfer Count Reload
register ( low/high byte, two's complement).
NOTE:
Registers 70h and 72h are slaved to registers A1h
and A2h unless Asynchronous mode is enabled (set bit 1
of register 71h).
5. Initialize and configure DAC: register 7Ah:
Register 7Ah:
Bit 2: Set high for signed, low for unsigned.
Bit 1: Set high for stereo data, low for mono.
Bit 0: Set high for 16-bit samples, low for 8-bit.
6. Set DMA and IRQ control registers B2h and 7Ah:
Register B2h: DRQ Configuration register.
Verify that bit 6 is high. Clear bits 7 and 5.
Register 7Ah: Audio 2 Control 2 register.
Bit 6 enables the audio 2 interrupt request.
7. Configure system interrupt controller and DMA
controller.
8. To start DMA:
Set bits 1:0 of register 78h high.
9. Delay approximately 100 milliseconds to allow analog
circuits to settle, then set the Audio 2 DAC playback
volume, register 7Ch.
10.During DMA:
For Auto-Initialize mode DMA transfers, read
Audio_Base+Eh to clear the interrupt request. Do not
send any other commands to the ES1879 at interrupt
time.
For Normal mode, initialize the system DMA controller
with the address and count of the next block to transfer.
Update the ES1879 Transfer Count registers if the
count is changed. To start the next transfer, clear bits
1:0 of register 78h, then set the bits high again.