Specifications

ESS Technology, Inc. SAM0023-122898 81
ES1869 DATA SHEET
TIMING DIAGRAMS
Figure 26 Compatibility Mode DMA Write Cycle
NOTE: In Compatibility mode DMA, the DMA request is reset by the acknowledge signal going low. In Extended mode
DMA, the DMA request is reset when the acknowledge signal is low AND the correct command signal is low – either
IORB (for DMA read from I/O device) or IOWB (for DMA writer to I/O device). For Extended mode DMA, the time t
10
is
relative to the later of the falling edge of the acknowledge signal, or the command signal.
Figure 27 Compatibility Mode DMA Read Cycle
DRQ
AEN
DACKB
IOWB
D[7:0]
t
11
t
8
t
9
t
10
t
12
t
6
t
7
DRQ
AEN
DACKB
IORB
D[7:0]
t
11
t
10
t
12
t
13
t
5
t
4