Specifications

48 SAM0023-122898 ESS Technology, Inc.
ES1869 DATA SHEET
PROGRAMMING THE ES1869
Bit 7 of port Audio_Base+Ch is the ES1869 Busy flag. It is
set when the write buffer is full or when the ES1869 is
otherwise busy (for example, during initialization after
reset or during Compatibility mode DMA requests).
To write a command or data byte to the ES1869
microcontroller:
1. Poll bit 7 of port Audio_Base+Ch until it is clear.
2. Write the command/data byte to port Audio_Base+Ch.
The following is an example of writing to ES1869 controller
registers. To set up the Audio 1 Transfer Count Reload
register to F800h, send the following command/data
bytes:
A4h, 00h; register A4h = 0h
A5h, F8h; register A5h = F8h
NOTE: The port Audio_Base+Ch write buffer is shared
with Compatibility mode DMA write operations. When
DMA is active, the Busy flag is cleared during windows of
time when a command can be received. Normally, the only
commands that should be sent during DMA operations are
Dxh commands such as DMA pause/continue and Audio 1
DAC enable/disable. In this situation it is recommended to
disable interrupts between the time that the Busy bit is
polled and the command is written. Also, minimize the time
between these instructions. See “Sending Commands
During DMA Operations” on page45 for more information.
Reading the Read Data Buffer of the ES1869
Command C0h is used to read the ES1869 controller
registers used for Extended mode. Send command C0h
followed by the register number, Axh or Bxh. For example,
to read register A4h, send the following command bytes:
C0h, A4h
Then poll the Read-Data-Buffer-Status bit, bit 7 of port
Audio_Base+Eh, before reading the register contents
from port Audio_Base+Ah.
The Read-Data-Buffer-Status flag can be polled by
reading bit 7 of port Audio_Base+Eh. When a byte is
available, the bit is set high.
NOTE: Any read of port Audio_Base+Eh also clears any
active interrupt request from the ES1869. An alternate
way of polling the Read-Data-Buffer-Status bit is through
bit 6 of port Audio_Base+Ch, which is the same flag. The
Read-Data-Buffer-Status flag is cleared automatically by
reading the byte from port Audio_Base+Ah.
Extended Mode Audio 1 DAC Operation
Follow the steps below to program the first audio channel
for Extended mode DAC operation:
1. Reset
Write 3h to port Audio_Base+6h, instead of 1h as in
Compatibility mode. Bit 1 high specifically clears the
FIFO. The remainder of the software reset is identical
to Compatibility mode. Reset disables the Audio 1 DAC
input to the mixer. This is intended to mask any pops
created during the setup of the DMA transfer.
2. After the reset, send command C6h to enable
Extended mode commands.
3. Program direction and type: registers B8h, A8h, and
B9h:
Register B8h: set bit 2 low for Normal DMA mode, high
for Auto-Initialize DMA mode. Leave bit 3 low for the
CODEC to run in the DAC direction.
Register A8h: read this register to preserve the bits and
then modify only bits 1 and 0:
Bits 1:0 10: Mono
Bits 1:0 01: Stereo
Set register B9h:
Bits 1:0 00: Single transfer DMA.
Bits 1:0 01: Demand Transfer DMA:
2 bytes per DMA request.
Bits 1:0 11: Demand transfer DMA:
4 bytes per DMA request.
4. Clocks and counters: registers A1h, A2h, A4h and A5h:
Register A1h: Sample Rate Clock Divider
Register A2h: Filter Clock Divider
Registers A4h/A5h: Audio 1 Transfer Count Reload
register low/high byte, two's complement
5. Initialize and configure DACs: registers B6h and B7h:
See Table 16.
Register B6h: 80h for signed data and 00h for unsigned
data. This also initializes the CODEC for DAC transfer.
Register B7h: programs the FIFO (16-bit/8-bit, signed/
unsigned, stereo/mono).