Specifications

ESS Technology, Inc. SAM0023-122898 41
ES1869 DATA SHEET
I/O PORTS
Read Data Register (Audio_Base+Ah, R)
Read data from embedded audio processor. Poll bit 7 of
port Audio_Base+Eh to test whether the register contents
are valid.
Write Data Register (Audio_Base+Ch, W)
Write data to embedded audio processor. Sets bit 7 of port
Audio_Base+Ch high (write buffer not available) until data
is processed by the ES1869.
Read Data Register (Audio_Base+Ch, R)
Bit Definitions:
Read Buffer Status Register (Audio_Base+Eh, R)
A read from port Audio_Base+Eh will reset any interrupt
request.
Bit Definitions:
Programmed I/O Access to FIFO Register
(Audio_Base+Fh, R/W)
This port can be used to replace Extended mode DMA
with programmed I/O.
FM Device
The FM synthesizer operates in two different modes:
Emulation mode and Native mode. In Emulation mode the
FM synthesizer is fully compatible with the OPL3 FM
synthesizer. In Native mode the FM synthesizer has
increased capabilities and performance for more realistic
music. The following register descriptions are for
Emulation mode only.
FM Status (FM_Base+0h, R)
Reading this register returns the overflow flags for timers
1 and 2 and the “interrupt request” from these timers (this
is not a real interrupt request but is supported as a status
flag for backward compatibility with the OPL3 FM
synthesizer).
FM Low Bank Address (FM_Base+0h, W)
Low bank register address.
NOTE: Any write to this register will also put the FM
synthesizer in Emulation mode if it is currently in Native
mode.
1 GPO1 1 = Set GPO1 high (Hardware reset condition).
0 = Clear GPO1.
0 GPO0 1 = Set GPO0 high.
0 = Clear GPO0 (Hardware reset condition).
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
Bits Name Description
7 BUSY
flag
1 = write buffer not available or ES1869 busy.
0 = write buffer available or ES1869 not busy.
6 1 = Data available in read buffer.
0 = Data not available in read buffer.
This flag is reset by a read from port
Audio_Base+Ah.
5 1 = Extended mode FIFO Full (256 bytes
loaded).
4 1 = Extended mode FIFO Empty (0 bytes
loaded).
3 1 = FIFO Half Empty, Extended mode flag.
2 1 = ES1869 processor generated an interrupt
request (e.g., from Compatibility mode DMA
complete).
1 1 = Interrupt request generated by FIFO Half
Empty flag change. Used by programmed I/O
interface to FIFO in Extended mode.
0 1 = Interrupt request generated by DMA
counter overflow in Extended mode.
Bits Name Description
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
Bits Name Description
7 1 = Data available in read buffer.
0 = Data not available in read buffer.
This flag is reset by a read from port
Audio_Base+Ah.
D7 D6 D5 D4 D3 D2 D1 D0
7 6 5 4 3 2 1 0
IRQ FT1 FT2 0 0 0 0 0
7 6 5 4 3 2 1 0
A7 A6 A5 A4 A3 A2 A1 A0
7 6 5 4 3 2 1 0