Data Sheet
Table Of Contents
- 1 Overview
- 2 Pin Definitions
- 3 Functional Description
- 4 Peripherals and Sensors
- 4.1 Descriptions of Peripherals and Sensors
- 4.1.1 General Purpose Input / Output Interface (GPIO)
- 4.1.2 Analog-to-Digital Converter (ADC)
- 4.1.3 Hall Sensor
- 4.1.4 Digital-to-Analog Converter (DAC)
- 4.1.5 Touch Sensor
- 4.1.6 Ultra-Low-Power Co-processor
- 4.1.7 Ethernet MAC Interface
- 4.1.8 SD/SDIO/MMC Host Controller
- 4.1.9 SDIO/SPI Slave Controller
- 4.1.10 Universal Asynchronous Receiver Transmitter (UART)
- 4.1.11 I²C Interface
- 4.1.12 I²S Interface
- 4.1.13 Infrared Remote Controller
- 4.1.14 Pulse Counter
- 4.1.15 Pulse Width Modulation (PWM)
- 4.1.16 LED PWM
- 4.1.17 Serial Peripheral Interface (SPI)
- 4.1.18 Accelerator
- 4.2 Peripheral Pin Configurations
- 4.1 Descriptions of Peripherals and Sensors
- 5 Electrical Characteristics
- 6 Package Information
- 7 Part Number and Ordering Information
- 8 Learning Resources
- Appendix A – ESP32 Pin Lists
- Revision History
1 Overview
• Defragmentation
• Automatic Beacon monitoring (hardware TSF)
• 4 × virtual Wi-Fi interfaces
• Simultaneous support for Infrastructure Station, SoftAP, and Promiscuous modes
Note that when ESP32 is in Station mode, performing a scan, the SoftAP channel will be changed.
• Antenna diversity
Note:
For more information, please refer to Section 3.5 Wi-Fi.
1.3 BT Key Features
• Compliant with Bluetooth v4.2 BR/EDR and BLE specifications
• Class-1, class-2 and class-3 transmitter without external power amplifier
• Enhanced Power Control
• +12 dBm transmitting power
• NZIF receiver with –94 dBm BLE sensitivity
• Adaptive Frequency Hopping (AFH)
• Standard HCI based on SDIO/SPI/UART
• High-speed UART HCI, up to 4 Mbps
• Bluetooth 4.2 BR/EDR BLE dual mode controller
• Synchronous Connection-Oriented/Extended (SCO/eSCO)
• CVSD and SBC for audio codec
• Bluetooth Piconet and Scatternet
• Multi-connections in Classic BT and BLE
• Simultaneous advertising and scanning
1.4 MCU and Advanced Features
1.4.1 CPU and Memory
• Xtensa
®
single-/dual-core 32-bit LX6 microprocessor(s), up to 600 MIPS (200 MIPS for
ESP32-S0WD/ESP32-U4WDH, 400 MIPS for ESP32-D2WD)
• 448 KB ROM
• 520 KB SRAM
• 16 KB SRAM in RTC
• QSPI supports multiple flash/SRAM chips
Espressif Systems 9
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ESP32 Series Datasheet v3.5