Data Sheet
Table Of Contents
- 1 Overview
- 2 Pin Definitions
- 3 Functional Description
- 4 Peripherals and Sensors
- 4.1 Descriptions of Peripherals and Sensors
- 4.1.1 General Purpose Input / Output Interface (GPIO)
- 4.1.2 Analog-to-Digital Converter (ADC)
- 4.1.3 Hall Sensor
- 4.1.4 Digital-to-Analog Converter (DAC)
- 4.1.5 Touch Sensor
- 4.1.6 Ultra-Low-Power Co-processor
- 4.1.7 Ethernet MAC Interface
- 4.1.8 SD/SDIO/MMC Host Controller
- 4.1.9 SDIO/SPI Slave Controller
- 4.1.10 Universal Asynchronous Receiver Transmitter (UART)
- 4.1.11 I²C Interface
- 4.1.12 I²S Interface
- 4.1.13 Infrared Remote Controller
- 4.1.14 Pulse Counter
- 4.1.15 Pulse Width Modulation (PWM)
- 4.1.16 LED PWM
- 4.1.17 Serial Peripheral Interface (SPI)
- 4.1.18 Accelerator
- 4.2 Peripheral Pin Configurations
- 4.1 Descriptions of Peripherals and Sensors
- 5 Electrical Characteristics
- 6 Package Information
- 7 Part Number and Ordering Information
- 8 Learning Resources
- Appendix A – ESP32 Pin Lists
- Revision History
5 Electrical Characteristics
5.3 DC Characteristics (3.3 V, 25 °C)
Table 13: DC Characteristics (3.3 V, 25 °C)
Symbol Parameter Min Typ Max Unit
C
IN
Pin capacitance - 2 - pF
V
IH
High-level input voltage 0.75×VDD
1
- VDD
1
+0.3 V
V
IL
Low-level input voltage –0.3 - 0.25×VDD
1
V
I
IH
High-level input current - - 50 nA
I
IL
Low-level input current - - 50 nA
V
OH
High-level output voltage 0.8×VDD
1
- - V
V
OL
Low-level output voltage - - 0.1×VDD
1
V
I
OH
High-level source current
(VDD
1
= 3.3 V,
V
OH
>= 2.64 V,
output drive strength set
to the maximum)
VDD3P3_CPU
power domain
1, 2
- 40 - mA
VDD3P3_RTC
power domain
1, 2
- 40 - mA
VDD_SDIO power
domain
1, 3
- 20 - mA
I
OL
Low-level sink current
(VDD
1
= 3.3 V, V
OL
= 0.495 V,
output drive strength set to the maximum)
- 28 - mA
R
P U
Resistance of internal pull-up resistor - 45 - kΩ
R
P D
Resistance of internal pull-down resistor - 45 - kΩ
V
IL_nRST
Low-level input voltage of CHIP_PU
to power off the chip
- - 0.6 V
Notes:
1. Please see Table IO_MUX for IO’s power domain. VDD is the I/O voltage for a particular power domain of pins.
2. For VDD3P3_CPU and VDD3P3_RTC power domain, per-pin current sourced in the same domain is gradually reduced
from around 40 mA to around 29 mA, V
OH
>=2.64 V, as the number of current-source pins increases.
3. For VDD_SDIO power domain, per-pin current sourced in the same domain is gradually reduced from around 30 mA to
around 10 mA, V
OH
>=2.64 V, as the number of current-source pins increases.
5.4 Reliability Qualifications
Table 14: Reliability Qualifications
Reliability tests Standards Test conditions Result
Electro-Static Discharge Sensitivity
(ESD), Charge Device Mode (CDM)
1
JEDEC EIA/JESD22-C101 ±500 V, all pins Pass
Electro-Static Discharge Sensitivity
(ESD), Human Body Mode (HBM)
2
JEDEC EIA/JESD22-A114 ±1500 V, all pins Pass
Latch-up (Over-current test) JEDEC STANDARD NO.78
±50 mA ~ ±200 mA, room
temperature, test for IO
Pass
Latch-up (Over-voltage test) JEDEC STANDARD NO.78
1.5 × Vmax, room temper-
ature, test for V
supply
Pass
Moisture Sensitivity Level (MSL) J-STD-020, MSL 3
30 °C, 60% RH, 192
hours, IR × 3 @260 °C
Pass
Espressif Systems 43
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ESP32 Series Datasheet v3.5