Data Sheet

3 Functional Description
• One of three or four possible actions (interrupt, CPU reset, core reset, and system reset) upon the expiry of
each stage
• 32-bit expiry counter
• Write protection that prevents the RWDT and MWDT configuration from being inadvertently altered
• SPI flash boot protection
If the boot process from an SPI flash does not complete within a predetermined time period, the watchdog
will reboot the entire system.
3.3 System Clocks
3.3.1 CPU Clock
Upon reset, an external crystal clock source is selected as the default CPU clock. The external crystal clock
source also connects to a PLL to generate a high-frequency clock (typically 160 MHz).
In addition, ESP32 has an internal 8 MHz oscillator. The application can select the clock source from the external
crystal clock source, the PLL clock or the internal 8 MHz oscillator. The selected clock source drives the CPU
clock directly, or after division, depending on the application.
3.3.2 RTC Clock
The RTC clock has five possible sources:
• external low-speed (32 kHz) crystal clock
• external crystal clock divided by 4
• internal RC oscillator (typically about 150 kHz, and adjustable)
• internal 8 MHz oscillator
• internal 31.25 kHz clock (derived from the internal 8 MHz oscillator divided by 256)
When the chip is in the normal power mode and needs faster CPU accessing, the application can choose the
external high-speed crystal clock divided by 4 or the internal 8 MHz oscillator. When the chip operates in the
low-power mode, the application chooses the external low-speed (32 kHz) crystal clock, the internal RC clock or
the internal 31.25 kHz clock.
3.3.3 Audio PLL Clock
The audio clock is generated by the ultra-low-noise fractional-N PLL. More details can be found in Chapter Reset
and Clock in the ESP32 Technical Reference Manual.
3.4 Radio
The radio module consists of the following blocks:
• 2.4 GHz receiver
• 2.4 GHz transmitter
• bias and regulators
Espressif Systems 26
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ESP32 Series Datasheet v3.5