Data Sheet
Table Of Contents
- 1 Overview
- 2 Pin Definitions
- 3 Functional Description
- 4 Peripherals and Sensors
- 4.1 Descriptions of Peripherals and Sensors
- 4.1.1 General Purpose Input / Output Interface (GPIO)
- 4.1.2 Analog-to-Digital Converter (ADC)
- 4.1.3 Hall Sensor
- 4.1.4 Digital-to-Analog Converter (DAC)
- 4.1.5 Touch Sensor
- 4.1.6 Ultra-Low-Power Co-processor
- 4.1.7 Ethernet MAC Interface
- 4.1.8 SD/SDIO/MMC Host Controller
- 4.1.9 SDIO/SPI Slave Controller
- 4.1.10 Universal Asynchronous Receiver Transmitter (UART)
- 4.1.11 I²C Interface
- 4.1.12 I²S Interface
- 4.1.13 Infrared Remote Controller
- 4.1.14 Pulse Counter
- 4.1.15 Pulse Width Modulation (PWM)
- 4.1.16 LED PWM
- 4.1.17 Serial Peripheral Interface (SPI)
- 4.1.18 Accelerator
- 4.2 Peripheral Pin Configurations
- 4.1 Descriptions of Peripherals and Sensors
- 5 Electrical Characteristics
- 6 Package Information
- 7 Part Number and Ordering Information
- 8 Learning Resources
- Appendix A – ESP32 Pin Lists
- Revision History
2 Pin Definitions
• GPIO0
• GPIO2
• MTDO
• GPIO5
Software can read the values of these five bits from register ”GPIO_STRAPPING”.
During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches of
the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is
powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of
VDD_SDIO and other initial system settings.
Each strapping pin is connected to its internal pull-up/pull-down during the chip reset. Consequently, if a
strapping pin is unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on the chip.
After reset release, the strapping pins work as normal-function pins.
Refer to Table 3 for a detailed boot-mode configuration by strapping pins.
Table 3: Strapping Pins
Voltage of Internal LDO (VDD_SDIO)
Pin Default 3.3 V 1.8 V
MTDI Pull-down 0 1
Booting Mode
Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
GPIO2 Pull-down Don’t-care 0
Enabling/Disabling Debugging Log Print over U0TXD During Booting
Pin Default U0TXD Active U0TXD Silent
MTDO Pull-up 1 0
Timing of SDIO Slave
Pin Default
FE Sampling
FE Output
FE Sampling
RE Output
RE Sampling
FE Output
RE Sampling
RE Output
MTDO Pull-up 0 0 1 1
GPIO5 Pull-up 0 1 0 1
Note:
• FE: falling-edge, RE: rising-edge.
• Firmware can configure register bits to change the settings of “Voltage of Internal LDO (VDD_SDIO)” and “Timing
of SDIO Slave”, after booting.
• For ESP32 chips that contain an embedded flash, users need to note the logic level of MTDI. For example, ESP32-
D2WD contains an embedded flash that operates at 1.8 V, therefore, the MTDI should be pulled high. ESP32-
U4WDH contains an embedded flash that operates at 3.3 V, therefore, the MTDI should be low.
Espressif Systems 20
Submit Documentation Feedback
ESP32 Series Datasheet v3.5