ESP32 Series Datasheet Including: ESP32-D0WD-V3 ESP32-D0WDQ6-V3 ESP32-D0WD ESP32-D0WDQ6 ESP32-D2WD ESP32-S0WD ESP32-U4WDH Version 3.5 Espressif Systems Copyright © 2021 www.espressif.
About This Guide This document provides the specifications of ESP32 family of chips. Document Updates Please always refer to the latest version on https://www.espressif.com/en/support/download/documents. Revision History For any changes to this document over time, please refer to the last page. Documentation Change Notification Espressif provides email notifications to keep customers updated on changes to technical documentation. Please subscribe at www.espressif.com/en/subscribe.
Contents Contents 1 Overview 8 1.1 Featured Solutions 8 1.1.1 Ultra-Low-Power Solution 8 1.1.2 Complete Integration Solution 8 1.2 Wi-Fi Key Features 8 1.3 BT Key Features 9 1.4 MCU and Advanced Features 9 1.4.1 CPU and Memory 9 1.4.2 Clocks and Timers 10 1.4.3 Advanced Peripheral Interfaces 10 1.4.4 Security 10 1.5 Applications (A Non-exhaustive List) 11 1.6 Block Diagram 12 2 Pin Definitions 13 2.1 Pin Layout 13 2.2 Pin Description 15 2.
Contents 3.6.2 Bluetooth Interface 29 3.6.3 Bluetooth Stack 29 3.6.4 Bluetooth Link Controller 29 3.7 RTC and Low-Power Management 30 4 Peripherals and Sensors 32 4.1 Descriptions of Peripherals and Sensors 32 4.1.1 General Purpose Input / Output Interface (GPIO) 32 4.1.2 Analog-to-Digital Converter (ADC) 32 4.1.3 Hall Sensor 33 4.1.4 Digital-to-Analog Converter (DAC) 33 4.1.5 Touch Sensor 33 4.1.6 Ultra-Low-Power Co-processor 33 4.1.7 Ethernet MAC Interface 34 4.1.
Contents 8 Learning Resources 50 8.1 Must-Read Documents 50 8.2 Must-Have Resources 50 Appendix A – ESP32 Pin Lists 51 A.1. Notes on ESP32 Pin Lists 51 A.2. GPIO_Matrix 53 A.3. Ethernet_MAC 58 A.4. IO_MUX 58 Revision History 60 Espressif Systems 5 Submit Documentation Feedback ESP32 Series Datasheet v3.
List of Tables List of Tables 1 Pin Description 15 2 Description of ESP32 Power-up and Reset Timing Parameters 19 3 Strapping Pins 20 4 Parameter Descriptions of Setup and Hold Times for the Strapping Pin 21 5 Memory and Peripheral Mapping 24 6 Power Consumption by Power Modes 30 7 ADC Characteristics 32 8 ADC Calibration Results 33 9 Capacitive-Sensing GPIOs Available on ESP32 33 10 Peripheral Pin Configurations 37 11 Absolute Maximum Ratings 42 12 Recommended Operating C
List of Figures List of Figures 1 Functional Block Diagram 12 2 ESP32 Pin Layout (QFN 6*6, Top View) 13 3 ESP32 Pin Layout (QFN 5*5, Top View) 14 4 ESP32 Power Scheme 18 5 ESP32 Power-up and Reset Timing 19 6 Setup and Hold Times for the Strapping Pin 21 7 Address Mapping Structure 23 8 QFN48 (6x6 mm) Package 48 9 QFN48 (5x5 mm) Package 48 10 ESP32 Part Number 49 Espressif Systems 7 Submit Documentation Feedback ESP32 Series Datasheet v3.
1 Overview 1 Overview ESP32 is a single 2.4 GHz Wi-Fi-and-Bluetooth combo chip designed with the TSMC ultra-low-power 40 nm technology. It is designed to achieve the best power and RF performance, showing robustness, versatility and reliability in a wide variety of applications and power scenarios.
1 Overview • Defragmentation • Automatic Beacon monitoring (hardware TSF) • 4 × virtual Wi-Fi interfaces • Simultaneous support for Infrastructure Station, SoftAP, and Promiscuous modes Note that when ESP32 is in Station mode, performing a scan, the SoftAP channel will be changed. • Antenna diversity Note: For more information, please refer to Section 3.5 Wi-Fi. 1.3 BT Key Features • Compliant with Bluetooth v4.
1 Overview 1.4.2 Clocks and Timers • Internal 8 MHz oscillator with calibration • Internal RC oscillator with calibration • External 2 MHz ~ 60 MHz crystal oscillator (40 MHz only for Wi-Fi/BT functionality) • External 32 kHz crystal oscillator for RTC with calibration • Two timer groups, including 2 × 64-bit timers and 1 × main watchdog in each group • One RTC timer • RTC watchdog 1.4.
1 Overview – RSA – ECC – Random Number Generator (RNG) 1.
1 Overview 1.
2 Pin Definitions 2 Pin Definitions CAP1 CAP2 VDDA XTAL_P XTAL_N VDDA GPIO21 U0TXD U0RXD GPIO22 GPIO19 VDD3P3_CPU 48 47 46 45 44 43 42 41 40 39 38 37 2.
CAP1 CAP2 VDDA XTAL_P XTAL_N VDDA GPIO21 U0TXD U0RXD GPIO22 48 47 46 45 44 43 42 41 40 39 2 Pin Definitions VDDA 1 38 GPIO19 LNA_IN 2 37 VDD3P3_CPU VDD3P3 3 36 GPIO23 VDD3P3 4 35 GPIO18 SENSOR_VP 5 34 GPIO5 SENSOR_CAPP 6 33 SD_DATA_1 SENSOR_CAPN 7 32 SD_DATA_0 SENSOR_VN 8 31 SD_CLK CHIP_PU 9 30 SD_CMD VDET_1 10 29 SD_DATA_3 VDET_2 11 28 SD_DATA_2 32K_XP 12 27 GPIO17 32K_XN 13 26 VDD_SDIO GPIO25 14 25 GPIO16 15 16 17 18 19 20
2 Pin Definitions Espressif Systems 2.2 Pin Description Table 1: Pin Description Name No. Type Function Analog Analog power supply (2.3 V ∼ 3.6 V) VDDA 1 P LNA_IN 2 I/O VDD3P3 3 P Analog power supply (2.3 V ∼ 3.6 V) VDD3P3 4 P Analog power supply (2.3 V ∼ 3.
No.
No. Type Function CAP1 48 I Connects to a 10 nF series capacitor to ground GND 49 P Ground Note: • The pin-pin mapping between ESP32-D2WD/ESP32-U4WDH and the embedded flash is as follows: GPIO16 = CS#, GPIO17 = IO1/DO, SD_CMD = IO3/HOLD#, SD_CLK = CLK, SD_DATA_0 = IO2/WP#, SD_DATA_1 = IO0/DI. The pins used for embedded flash are not recommended for other uses.
2 Pin Definitions 2.3 Power Scheme ESP32’s digital pins are divided into three different power domains: • VDD3P3_RTC • VDD3P3_CPU • VDD_SDIO VDD3P3_RTC is also the input power supply for RTC and CPU. VDD3P3_CPU is also the input power supply for CPU. VDD_SDIO connects to the output of an internal LDO whose input is VDD3P3_RTC. When VDD_SDIO is connected to the same PCB net together with VDD3P3_RTC, the internal LDO is disabled automatically. The power scheme diagram is shown below: VDD3P3_RTC 1.
2 Pin Definitions t0 t1 VDD3P3_RTC Min VDD VIL_nRST CHIP_PU Figure 5: ESP32 Powerup and Reset Timing Table 2: Description of ESP32 Powerup and Reset Timing Parameters Parameters t0 t1 Description Time between the 3.3 V rails being brought up and CHIP_PU being activated Duration of CHIP_PU signal level < VIL_nRST (refer to its value in Table 13 DC Characteristics) to reset the chip Min.
2 Pin Definitions • GPIO0 • GPIO2 • MTDO • GPIO5 Software can read the values of these five bits from register ”GPIO_STRAPPING”. During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of VDD_SDIO and other initial system settings.
2 Pin Definitions The illustration below shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high. Details about the parameters are listed in Table 4. t0 CHIP_PU t1 VIL_nRST VIH Strapping pin Figure 6: Setup and Hold Times for the Strapping Pin Table 4: Parameter Descriptions of Setup and Hold Times for the Strapping Pin Parameters Description Min.
3 Functional Description 3 Functional Description This chapter describes the functions integrated in ESP32. 3.1 CPU and Memory 3.1.
3 Functional Description 3.1.3 External Flash and SRAM ESP32 supports multiple external QSPI flash and SRAM chips. More details can be found in Chapter SPI in the ESP32 Technical Reference Manual. ESP32 also supports hardware encryption/decryption based on AES to protect developers’ programs and data in flash. ESP32 can access the external QSPI flash and SRAM through high-speed caches. • Up to 16 MB of external flash can be mapped into CPU instruction memory space and read-only memory space simultaneously.
3 Functional Description Table 5: Memory and Peripheral Mapping Category Embedded Memory Target Start Address End Address Size Internal ROM 0 0x4000_0000 0x4005_FFFF 384 KB Internal ROM 1 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal SRAM 0 0x4007_0000 0x4009_FFFF 192 KB 0x3FFE_0000 0x3FFF_FFFF 0x400A_0000 0x400B_FFFF 0x3FFA_E000 0x3FFD_FFFF 0x3FF8_0000 0x3FF8_1FFF 0x400C_0000 0x400C_1FFF 0x5000_0000 0x5000_1FFF 8 KB 0x3F40_0000 0x3F7F_FFFF 4 MB Internal SRAM 1 Internal SRAM 2 RT
3 Functional Description Category Peripheral Target Start Address End Address Size SYSCON 0x3FF6_6000 0x3FF6_6FFF 4 KB I2C1 0x3FF6_7000 0x3FF6_7FFF 4 KB SDMMC 0x3FF6_8000 0x3FF6_8FFF 4 KB EMAC 0x3FF6_9000 0x3FF6_AFFF 8 KB PWM1 0x3FF6_C000 0x3FF6_CFFF 4 KB I2S1 0x3FF6_D000 0x3FF6_DFFF 4 KB UART2 0x3FF6_E000 0x3FF6_EFFF 4 KB PWM2 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM3 0x3FF7_0000 0x3FF7_0FFF 4 KB RNG 0x3FF7_5000 0x3FF7_5FFF 4 KB 3.2 Timers and Watchdogs 3.2.
3 Functional Description • One of three or four possible actions (interrupt, CPU reset, core reset, and system reset) upon the expiry of each stage • 32-bit expiry counter • Write protection that prevents the RWDT and MWDT configuration from being inadvertently altered • SPI flash boot protection If the boot process from an SPI flash does not complete within a predetermined time period, the watchdog will reboot the entire system. 3.3 System Clocks 3.3.
3 Functional Description • balun and transmit-receive switch • clock generator 3.4.1 2.4 GHz Receiver The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits and baseband filters are integrated in the chip. 3.4.2 2.4 GHz Transmitter The 2.
3 Functional Description • 802.11b/g/n • 802.11n MCS0-7 in both 20 MHz and 40 MHz bandwidth • 802.11n MCS32 (RX) • 802.11n 0.4 µs guard-interval • up to 150 Mbps of data rate • Receiving STBC 2×1 • Up to 20.5 dBm of transmitting power • Adjustable transmitting power • Antenna diversity ESP32 supports antenna diversity with an external RF switch. One or more GPIOs control the RF switch and selects the best antenna to minimize the effects of channel fading. 3.5.
3 Functional Description • Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping • ACL, SCO, eSCO and AFH • A-law, µ-law and CVSD digital audio CODEC in PCM interface • SBC audio CODEC • Power management for low-power applications • SMP with 128-bit AES 3.6.
3 Functional Description – Ping • Bluetooth Low Energy – Advertising – Scanning – Simultaneous advertising and scanning – Multiple connections – Asynchronous data reception and transmission – Adaptive Frequency Hopping and Channel assessment – Connection parameter update – Data Length Extension – Link Layer Encryption – LE Ping 3.7 RTC and LowPower Management With the use of advanced power-management technologies, ESP32 can switch between different power modes.
3 Functional Description Power mode Description Normal speed: 80 MHz Light-sleep Deep-sleep Dual-core chip(s) 20 mA ~ 31 mA Single-core chip(s) 20 mA ~ 25 mA - 0.8 mA The ULP co-processor is powered on. 150 µA ULP sensor-monitored pattern 100 µA @1% duty RTC timer + RTC memory 10 µA RTC timer only 5 µA CHIP_PU is set to low level, the chip is powered off.
4 Peripherals and Sensors 4 Peripherals and Sensors 4.1 Descriptions of Peripherals and Sensors 4.1.1 General Purpose Input / Output Interface (GPIO) ESP32 has 34 GPIO pins which can be assigned various functions by programming the appropriate registers. There are several kinds of GPIOs: digital-only, analog-enabled, capacitive-touch-enabled, etc. Analog-enabled GPIOs and Capacitive-touch-enabled GPIOs can be configured as digital GPIOs.
4 Peripherals and Sensors Table 8: ADC Calibration Results Parameter Total error Description Min Max Unit Atten=0, effective measurement range of 100 ∼ 950 mV –23 23 mV Atten=1, effective measurement range of 100 ∼ 1250 mV –30 30 mV Atten=2, effective measurement range of 150 ∼ 1750 mV –40 40 mV Atten=3, effective measurement range of 150 ∼ 2450 mV –60 60 mV 4.1.3 Hall Sensor ESP32 integrates a Hall sensor based on an N-carrier resistor.
4 Peripherals and Sensors 4.1.7 Ethernet MAC Interface An IEEE-802.3-2008-compliant Media Access Controller (MAC) is provided for Ethernet LAN communications. ESP32 requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to ESP32 through 17 signals of MII or nine signals of RMII.
4 Peripherals and Sensors • Interrupts to host for initiating data transfer • Automatic loading of SDIO bus data and automatic discarding of padding data • Block size of up to 512 bytes • Interrupt vectors between the host and the slave, allowing both to interrupt each other • Supports DMA for data transfer 4.1.10 Universal Asynchronous Receiver Transmitter (UART) ESP32 has three UART interfaces, i.e.
4 Peripherals and Sensors 4.1.15 Pulse Width Modulation (PWM) The Pulse Width Modulation (PWM) controller can be used for driving digital motors and smart lights. The controller consists of PWM timers, the PWM operator and a dedicated capture sub-module. Each timer provides timing in synchronous or independent form, and each PWM operator generates a waveform for one PWM channel. The dedicated capture sub-module can accurately capture events with external timing. 4.1.
4 Peripherals and Sensors 4.
4 Peripherals and Sensors Interface Signal Pin Function HS2_CLK MTMS HS2_CMD MTDO SD/SDIO/MMC Host HS2_DATA0 GPIO2 Controller HS2_DATA1 GPIO4 HS2_DATA2 MTDI HS2_DATA3 MTCK Supports SD memory card V3.01 standard PWM0_OUT0~2 PWM1_OUT_IN0~2 Three channels of 16-bit timers generate PWM0_FLT_IN0~2 Motor PWM PWM1_FLT_IN0~2 PWM0_CAP_IN0~2 PWM waveforms.
4 Peripherals and Sensors Interface LED PWM Signal Pin ledc_hs_sig_out0~7 ledc_ls_sig_out0~7 Function Any GPIO Pins 16 independent channels @80 MHz clock/RTC CLK. Duty accuracy: 16 bits.
4 Peripherals and Sensors Interface Parallel QSPI EMAC Signal Pin Function SPIHD SD_DATA_2 SPIWP SD_DATA_3 SPICS0 SD_CMD SPICLK SD_CLK SPIQ SD_DATA_0 SPID SD_DATA_1 HSPICLK MTMS HSPICS0 MTDO HSPIQ MTDI HSPID MTCK HSPIHD GPIO4 HSPIWP GPIO2 VSPICLK GPIO18 VSPICS0 GPIO5 VSPIQ GPIO19 VSPID GPIO23 VSPIHD GPIO21 VSPIWP GPIO22 EMAC_TX_CLK GPIO0 EMAC_RX_CLK GPIO5 EMAC_TX_EN GPIO21 EMAC_TXD0 GPIO19 EMAC_TXD1 GPIO22 EMAC_TXD2 MTMS EMAC_TXD3 MTDI EMAC_RX_ER MTC
4 Peripherals and Sensors Interface Signal Pin Function pcnt_sig_ch0_in0 pcnt_sig_ch1_in0 pcnt_ctrl_ch0_in0 pcnt_ctrl_ch1_in0 pcnt_sig_ch0_in1 pcnt_sig_ch1_in1 pcnt_ctrl_ch0_in1 pcnt_ctrl_ch1_in1 pcnt_sig_ch0_in2 pcnt_sig_ch1_in2 pcnt_ctrl_ch0_in2 pcnt_ctrl_ch1_in2 pcnt_sig_ch0_in3 pcnt_sig_ch1_in3 pcnt_ctrl_ch0_in3 Pulse Counter pcnt_ctrl_ch1_in3 pcnt_sig_ch0_in4 Operating in seven different modes, the Any GPIO Pins pulse counter captures pulse and counts pulse edges.
5 Electrical Characteristics 5 Electrical Characteristics 5.1 Absolute Maximum Ratings Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the device. These are stress ratings only, and do not refer to the functional operation of the device that should follow the recommended operating conditions.
5 Electrical Characteristics 5.3 DC Characteristics (3.3 V, 25 °C) Table 13: DC Characteristics (3.3 V, 25 °C) Symbol Min Typ Pin capacitance - 2 VIH High-level input voltage 1 - VDD +0.3 V VIL Low-level input voltage –0.3 - 0.25×VDD1 V IIH High-level input current - - 50 nA IIL Low-level input current - - 50 nA VOH High-level output voltage 0.8×VDD1 - - V VOL Low-level output voltage - - 0.
5 Electrical Characteristics 1. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 2. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 5.5 RF PowerConsumption Specifications The power consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 50% duty cycle.
5 Electrical Characteristics 5.7 Bluetooth Radio 5.7.1 Receiver – Basic Data Rate Table 17: Receiver Characteristics – Basic Data Rate Parameter Conditions Min Typ Max Unit Sensitivity @0.1% BER - –90 –89 –88 dBm Maximum received signal @0.
5 Electrical Characteristics 5.7.3 Receiver – Enhanced Data Rate Table 19: Receiver Characteristics – Enhanced Data Rate Parameter Conditions Min Typ Max Unit π/4 DQPSK Sensitivity @0.01% BER - –90 –89 –88 dBm Maximum received signal @0.
5 Electrical Characteristics Parameter Conditions In-band spurious emissions EDR differential phase coding Min Typ Max Unit F = F0 ± 1 MHz - –46 - dBm F = F0 ± 2 MHz - –40 - dBm F = F0 ± 3 MHz - –46 - dBm F = F0 +/– > 3 MHz - - –53 dBm - - 100 - % 5.8 Bluetooth LE Radio 5.8.1 Receiver Table 21: Receiver Characteristics – BLE Parameter Conditions Min Typ Max Unit Sensitivity @30.8% PER - –94 –93 –92 dBm Maximum received signal @30.
6 Package Information 6 Package Information Pin 1 Pin 2 Pin 3 Pin 1 Pin 2 Pin 3 Figure 8: QFN48 (6x6 mm) Package 3 2 1 Pin 1 Pin 2 Pin 3 Figure 9: QFN48 (5x5 mm) Package Note: The pins of the chip are numbered in an anti-clockwise direction from Pin 1 in the top view. Espressif Systems 48 Submit Documentation Feedback ESP32 Series Datasheet v3.
7 Part Number and Ordering Information 7 Part Number and Ordering Information ESP32 - D 0 WD H Q6 V3 Wafer version 3 Package Q6=QFN 6*6 N/A=QFN 5*5 Connection WD=Wi-Fi b/g/n + BT/BLE dual mode Embedded flash 0=No embedded flash 2=2 MB flash 4=4 MB flash Core D=Dual core S =Single core Figure 10: ESP32 Part Number The table below provides the ordering information of the ESP32 series of chips.
8 Learning Resources 8 Learning Resources 8.1 MustRead Documents Click on the following links to access documents related to ESP32. • ESP32 ECO V3 User Guide This document describes differences between V3 and previous ESP32 silicon wafer revisions. • ECO and Workarounds for Bugs in ESP32 This document details hardware errata and workarounds in the ESP32. • ESP-IDF Programming Guide It hosts extensive documentation for ESP-IDF, ranging from hardware guides to API reference.
Appendix A Appendix A – ESP32 Pin Lists A.1. Notes on ESP32 Pin Lists Table 24: Notes on ESP32 Pin Lists No. 1 Description In Table IO_MUX, the boxes highlighted in yellow indicate the GPIO pins that are input-only. Please see the following note for further details. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- 2 up/pull-down circuitry.
Appendix A No. Description Each column about digital “Function” is accompanied by a column about “Type”. Please see the following explanations for the meanings of “type” with respect to each “function” they are associated with. For each “Function-N”, “type” signifies: • I: input only. If a function other than “Function-N” is assigned, the input signal of “Function-N” is still from this pin. • I1: input only. If a function other than “Function-N” is assigned, the input signal of “Function-N” is always “1”.
Appendix A No. Description *In Table GPIO_Matrix�the column “Default Value if unassigned” records the default value of 13 the an input signal if no GPIO is assigned to it. The actual value is determined by register GPIO_FUNCm_IN_INV_SEL and GPIO_FUNCm_IN_SEL. (The value of m ranges from 1 to 255.) A.2. GPIO_Matrix Table 25: GPIO_Matrix Signal No.
Appendix A Signal No.
Appendix A Signal No.
Appendix A Signal No.
Appendix A Signal No.
Appendix A Signal No. Input signals Default Same input value if signal from unassigned* Output enable of IO_MUX core Output signals output signals 226 - - - sig_in_func226 1’d1 227 - - - sig_in_func227 1’d1 228 - - - sig_in_func228 1’d1 A.3.
Pin No.
Revision History Revision History Date Version Release notes Updated the description for CAP2 from 3 nF to 3.3 nF 2021-01-22 V3.5 Added TWAI® in Section 1.4.3: Advanced Peripheral Interfaces Updated Figure 1: Functional Block Diagram Updated the reset values for MTCK, MTMS, GPIO27 in Appendix IO_MUX Added one chip variant: ESP32-U4WDH 2020-04-27 V3.4 Updated some figures in Table 6, 16, 17, 19, 21, 22 Added a note under Table 18 2020.01 V3.3 2019.10 V3.
Revision History Date Version Release notes • Changed the voltage range of VDD3P3_RTC from 1.8-3.6V to 2.3-3.6V in Table 1: Pin Description; • Updated Section 2.3: Power Scheme; • Updated Section 3.1.3: External Flash and SRAM; • Updated Table 6: Power Consumption by Power Modes; • Deleted content about temperature sensor; Changes to electrical characteristics: • Updated Table 11: Absolute Maximum Ratings; 2018.05 V2.
Revision History Date Version Release notes • Changed the transmitting power to +12 dBm; the sensitivity of NZIF receiver to -97 dBm in Section 1.3; • Added a note to Table 1 Pin Description; • Added 160 MHz clock frequency in section 3.1.1; • Changed the transmitting power from 21 dBm to 20.5 dBm in Section 3.5.
Revision History Date Version 2017.03 V1.2 Release notes • Added a note to Table: Pin Description; • Updated the note in Section: Internal Memory. • Added Chapter: Part Number and Ordering Information; • Updated Section: MCU and Advanced Features; • Updated Section: Block Diagram; • Updated Chapter: Pin Definitions; 2017.02 V1.
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