User's Manual

2.
Pin Definitions
2.3 Strapping Pins
ESP32 has five strapping pins: MTDI, GPIO0, GPIO2, MTDO, GPIO5. The pin-pin mapping between ESP32 and
the module is as follows, which can be seen in Chapter 5 Schematics:
• MTDI = IO12
• GPIO0 = BOOT/IO0
• GPIO2 = IO2
• MTDO = IO15
• GPIO5 = IO5
Software can read the values of these five bits from register ”GPIO_STRAPPING”.
During the chip’s system reset release (power-on-reset, RTC watchdog reset and brownout reset), the latches
of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip
is powered down or shut down. The strapping bits configure the device’s boot mode, the operating voltage of
VDD_SDIO and other initial system settings.
Each strapping pin is connected to its internal pull-up/pull-down during the chip reset. Consequently, if a strapping
pin is unconnected or the connected external circuit is high-impedance, the internal weak pull-up/pull-down will
determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32.
After reset release, the strapping pins work as normal-function pins.
Refer to Table 2 for a detailed boot-mode configuration by strapping pins.
Table 2: Strapping Pins
Voltage of Internal LDO (VDD_SDIO)
Pin Default 3.3 V 1.8 V
MTDI Pull-down 0 1
Booting Mode
Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
GPIO2 Pull-down Don’t-care 0
Enabling/Disabling Debugging Log Print over U0TXD During Booting
Pin Default U0TXD Active U0TXD Silent
MTDO Pull-up 1 0
Timing of SDIO Slave
Pin Default
FE Sampling
FE Output
FE Sampling
RE Output
RE Sampling
FE Output
RE Sampling
RE Output
MTDO Pull-up 0 0 1 1
GPIO5 Pull-up 0 1 0 1
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