Specifications

19A705178
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ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
K P Dotson 11-19-86
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
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R96FT Interface Memory Definitions (Continued)
Mnemonic Name
Memory
Location Description
(None) Transmitter Data 0:0:0-7 The host processor conveys output data to the transmitter in the parallel mode by writing a data byte
to the transmitter data register. The data is divided on baud boundaries, as follows:
Note: Data is transmitted bit zero first.
Bits
Configuration 76543210
V.29 9600 bps Baud 1 Baud 0
V.29 7200 bps Not Used Baud 1 Baud 0
V.29 4800 bps Baud 3 Baud 2 Baud 1 Baud 0
V.27 4800 bps Not Used Baud 1 Baud 0
V.27 2400 bps Baud 3 Baud 2 Baud 1 Baud 0
2400 bps Gearshift Baud 3 Baud 2 Baud 1 Baud 0
4800 bps Gearshift Baud 1 Baud 0
TSB Transmitter Setup 0:E:3 When the host processor changes the transmitter configuration, the SEPT bit or the FSKT bit, the host
must write a one in this control bit. TSB goes to a zero when the change becomes effective. Worst
case setup time is 2 baud + turnoff sequence + training (if applicable).
TTDIS Transmitter Train
Disable
0:7:6 When control bit TTDIS is a one, the transmitter does not generate a training sequence at the start of
transmission. With training disabled, RTS/CTS delay is less than two baud times.
XCEN External Clock
Enable
0:7:1 When control bit XCEN is a one, the transmitter timing is established by the external clock supplied
at the hardware input XTCLK, pin 22A.
POWER-ON INITIALIZATION
When power is applied to the R96FT, a period of 50 to 350
ms is required for power supply settling. The power-on-
reset signal (POR) remains low during this period.
Approximately 10 ms after the low to high transition of
POR, the modem is ready to be configured, and RTS may
be activated. If the 5 Vdc power supply drops below 3.5
Vdc for more than 30 msec, the POR cycle is generated.
At POR time the modem defaults to the following
configuration: fast train, V.29, 9600 bps, no echo protector
tone, 1700 Hz carrier frequency, scrambled ones segment
disabled, serial data mode, internal clock, cable equalizers
disabled, transmitter digital delay equalizer disabled,
transmitter output level set to -1 dBm ± 1 dB, interrupts
disabled, receiver threshold set to -43 dBm, and train-on-
data enabled.
POR can be connected to a user supplied power-on-reset
signal in a wire-or configuration. A low active pulse of 3
µsec or more applied to the POR pin causes the modem to
reset. The modem is ready to be configured 10 msec after
POR is removed.
PERFORMANCE
Whether functioning in V.27, V.29 or the proprietary fast
train configurations, the R96FT provides the user with high
performance.
Polling Success
In the 9600 bps fast train configuration the modem
approaches a 98% success rate over unconditioned 3002
lines for a signal-to-noise ratio of 26 dB, with a received
signal level of -20 dBm.
Bit Error Rates
The Bit Error Rate (BER) performance of the modem is
specified for a test configuration conforming to that
specified in CCITT Recommendation V.56. Bit error rates
are measured at a received line signal level of -20 dBm as
illustrated.
Phase Jitter
At 2400 bps, the modem exhibits a bit error rate of 10
-6
or
less with a signal-to-noise ratio of 12.5 dB in the presence
REVISIONS
L30
PRINTS TO