Specifications

19A705178
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ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
K P Dotson 11-19-86
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
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R96FT Interface Memory Definitions (Continued)
Mnemonic Name
Memory
Location Description
(None) Receiver
Configuration
1:6:0-6
The host processor configures the receiver by writing a control code into the receiver configuration
field in the interface memory space (see RSB).
Note:
The receiver must be disabled prior to changing configurations. See RDIS.
Receiver Configuration Control Codes
Control codes for the modem receiver configuration are:
Configuration
V.29 V.27 bis/ter Configuration Code (Hex)
FT/9600
FT/7200
FT/4800
FT/4800
FT/2400
1C
1A
19
0A
09
9600
7200
4800
4800 long
2400 long
4800 short
2400 short
14
12
11
22
21
02
01
2400/4800 bps Gearshift/V.29 descrambler
2400/4800 bps Gearshift/V.27 bis/ter descrambler
61
1
41
1
V.21 Channel 2 See Note 2
1. The Receiver Configuration code automatically changes from a hex 61 (or hex 41) to a hex 64 (or
hex 44) when the receiver transitions from the 2400 bps data state to the 4800 bps data state.
2. The FSK receiver is active at all times. Two ancillary hardware circuits, FRLSD and FRXD, are
supplied for FSK message reception. FRLSD is described under the Received Line Signal
Detector section. FRXD provides inverted FSK received data. Timing extraction must be performed
on the FRXD signal externally as no FSK receiver data clock is provided by the R96FT.
(None) Receiver Data 1:0:0-7 The host processor obtains channel data from the receiver in the parallel data mode by reading a data
byte from the receiver data register. The data is divided on baud boundaries as is the transmitter data.
RDA Receiver Data
Available
1:E:0 Status bit RDA goes to a one when the receiver writes data to register 1:0. RDA goes to a zero when
the host processor reads data from register 1:0.
RDIS Receiver Disable 1:7:1 When control bit RDIS is a one, the receiver is disabled, RLSD is turned off and RXD is clamped to
all marks. This bit can be used to squelch the receiver during half duplex transmissions over two
wires. This bit must be set to a one prior to changing the receiver configuration.
RIA Receiver Interrupt
Active
1:E:7 This status bit is a one whenever the receiver sample rate device is driving IRQ to zero.
RIE Receiver Interrupt
Enable
1:E:2 When the host processor writes a one in the RIE control bit, the IRQ line of the hardware interface is
driven to zero when status bit RDA is a one.
RSB Receiver Setup Bit 1:E:3 When the host processor changes the receiver configuration or the RTH field, the host processor must
write a one in the RSB control bit. RSB goes to zero when the changes become effective
RTH Receiver Threshold
Field
1:7:6,7 The receiver energy detector threshold is set by the RTH field according to the following codes (see
RSB):
RTH RLSD On RLSD Off
0
≥
43 dBm
≥
48 dBm
1
≥
33 dBm
≥
38 dBm
2
≥
26 dBm
≥
31 dBm
3
≥
16 dBm
≥
21 dBm
RTS Request-to-Send 0:7:7 When control bit RTS goes to a one, the modem begins a transmit sequence. It continues to transmit
until RTS is reset to zero, and the turn-off sequence has been completed. This input bit parallels the
operation of the hardware RTS control input. These inputs are OR’ed by the modem.
REVISIONS
L30
PRINTS TO