Specifications

19A705178
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ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
K P Dotson 11-19-86
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
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R96FT Interface Memory Definitions (Continued)
Mnemonic Name
Memory
Location Description
LAEN Link Amplitude
Equalizer Enable
0:5:3 The link amplitude equalizer enable and select bits control an amplitude compromise equalizer in the
receive path according to the following table:
LAEN A3L Curve Matched
0 X No Equalizer
1 0 U.S. Survey Long
1 1 Japanese 3-Link
LCEN Loop Clock Enable 0:4:0 When control bit LCEN is a one, the transmitter clock tracks the receiver clock.
LDEN Link Delay
Equalizer Enable
0:5:2 The link delay equalizer enable and select bits control a delay compromise equalizer in the receiver
path according to the following table:
LDEN D3L Curve Matched
0 X No Equalizer
1 0 U.S. Survey Long
1 1 Japanese 3-Link
L2ACT Remote Digital
Loopback Activate
0:4:1 When control bit L2ACT is a one, the receiver digital output is connected to the transmitter digital
input in accordance with CCITT Recommendation V.54 loop 2.
L3ACT Local Analog Loop-
back Activate
0:4:7 When control bit L3ACT is a one, the transmitter analog output is coupled to the receiver analog input
through an attenuator in accordance with CCITT Recommendation V.54 loop 3.
L4ACT Remote Analog
Loopback Activate
0:4:6 When control bit L4ACT is a one, the receiver analog input is connected to the transmitter analog
output through a variable gain amplifier in a manner similar to CCITT Recommendation V.54 loop 4.
L4HG Loop 4 High Gain 0:4:5 When control bit L4HG is a one, the loop 4 variable gain amplifier is set for +16 dB, and when at zero
the gain is zero dB.
MHLD Mark Hold 0:7:4 When control bit MHLD is a one, the transmitter input data stream is forced to all marks (ones).
P2DET Period 2 Detector 1:8:3 When status bit P2DET is a zero, it indicates that a period 2 sequence has been detected. This bit sets
to a one at the start of the period N sequences. This bit is only significant for CCITT V.29 and V.27
bis/ter configurations.
(None) RAM Access X 2:5:0-7 Contains the RAM access code used in reading chip 2 RAM locations via word X (2:3 and 2:2)
(None) RAM Access Y 2:5:0-7 Contains the RAM access code used in reading chip 2 RAM locations via word Y (2:3 and 2:2)
(None) RAM Data XL 2:2:0-7 Least significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None) RAM Data XM 2:3:0-7 Most significant byte of 16-bit word X used in reading RAM locations in chip 2.
(None) RAM Data YL 2:0:0-7 Least significant byte of 16-bit word Y used in reading RAM locations in chip 2.
(None) RAM Data YM 2:1:0-7 Most significant byte of 16-bit word Y used in reading RAM locations in chip 2.
RBDA Receiver Baud
Data Available
2:E:0 Status bit RBDA goes to a one when the receiver writes data into register 2:0. The bit goes to a zero
when the host processor reads data from register 2:0.
RBIA Receiver Baud
Interrupt Active
2:E:7 This status bit is a one whenever the receiver baud rate device is driving IRQ low.
RBIE Receiver Baud
Interrupt Enable
2:E:2 When the host processor writes a one in the RBIE control bit, the IRQ line of the hardware interface is
driven to zero when status bit RBDA is a one.
RCR Receiver Carrier
Frequency
1:7:2 Control bit RCF selects the demodulator carrier frequency for V.29FT configurations as follows:
RCF Demodulator Carrier Frequency
0 1700 Hz
1 1800 Hz
REVISIONS
L30
PRINTS TO