Specifications
19A705178
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ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
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F. C. F. O.
MADE BY
K P Dotson 11-19-86
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
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R96FT Interface Memory Definitions
Mnemonic Name
Memory
Location Description
ASCR Append Scrambled
Ones
0:9:6 When control bit ASCR is a one, one baud of scrambled marks is included in the V.29 FT and V.27
FT training sequences The RTS-CTS delay is thus extended by one baud per when ASCR is a one.
A3L Amplitude 3-Link
Select
0:5:1 See LAEN.
CDET Carrier Detector 1:9:2 When zero, status bit CDET indicates that passband energy is being detected, and that a training
sequence is not in process. CDET goes to a zero at the start of the data state, and returns to a one at
the end of the received signal. CDET activates up to 1 baud time before RLSD and deactivates within
2 baud times after RLSD.
CEQ Cable Equalizer 0:5:(4,5) The CEQ Control field simultaneously controls amplitude compromise equalizers in both the transmit
and receive paths. The following table lists the possible cable equalizer selection codes:
CEQ Cable Length (0.4 mm diameter)
0 0.0
1 1.8 km
2 3.6 km
3 7.2 km
DDEE Digital Delay
Equalizer Enable
0:9:2 When control bit DDEE is a one, a fourth order digital delay equalizer is inserted in the transmit path.
DDIS Descramble Disable 1:7:5 When control bit DDIS is a one, the receiver descrambler circuit is removed from the data path.
D3L Delay 3-Link Select 0:5:0 See LDEN.
EPT Echo Protector
Tone
0:7:3 When control bit EPT is a one, an unmodulated carrier is transmitted for 185 ms (optionally 30 ms)
followed by 20 ms of no transmitted energy at the start of transmission. This option is available in the
V.27 and V.29 configurations, although it is not specified in the CCITT V.29 Recommendation.
FED Fast Energy
Detector
1:9:6 When status bit FED is a zero, it indicates that energy above the receiver threshold is present in the
passband
(None) FREQL/FREQM 0:2:0-7
0:3:0-7
The host processor conveys tone generation data to the transmitter by writing a 16-bit data word to the
FREQL and FREQM registers in the interface memory space, as shown below:
FREQM Register (0:3)
Bit:
76543210
Data Word:
2
15
2
14
2
13
2
12
2
11
2
10
2
9
2
8
FREQL Register (0:2)
Bit:
76543210
Data Word:
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
The frequency number (N) determines the frequency (F) as follows:
F = (0.146486) (N) Hz
±
0.01%
Hexadecimal frequency numbers (FREQL, FREQM) for commonly generated tones are given below:
Frequency (Hz) FREQM FREQL
462 0C 52
1100 1D 55
1650 2C 00
1850 31 55
2100 38 00
FSKT FSK Transmitter
Configuration
0:9:7 The V.21 Channel 2 (300 bps synchronous FSK) transmitter configuration is selected by setting the
FSKT control bit to a one (see TSB). While set to a one, this control bit overrides the configuration
selected by the control code in register 0:6. The FSK data may be transmitted in parallel mode or in
serial mode (see TPDM).
REVISIONS
L30
PRINTS TO