Specifications

19A705178
REV NO. TITLE
CONT ON SHEET
18
SH NO.
17
ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
R Sager
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
CONT ON SHEET
18
SH NO.
17
Reading of diagnostic RAM data is performed by storing
the necessary access codes in 2:5 and 2:4, reading 2:0 to
reset the associated data available bit (2:E:0), then waiting
for the data available bit to return to a one. Data is now
valid and may be read from 2:3 through 2:0.
An additional diagnostic is supplied by the sample rate
processor (chip 1). Registers 1:2 and 1:3 supply a 16 bit
AGC Gain Word. These two diagnostic data registers are
updated at the sample rate during the data state and may be
read by the host processor asynchronously.
RAM Access Codes
The RAM access codes defined in the following table
allow the host processor to read diagnostic information
within the modem.
Baud Rate Processor (Chip 2) RAM Access Codes
No. Function X Access Y Access Register
1 Equalizer Input C0 40 0,1,2,3
2 Equalizer Tap Coefficients 81-A0 01-20 0,1,2,3
3 Unrotated Equalizer Output E1 61 0,1,2,3
4 Rotated Equalizer Output E2 62 0,1,2,3
5 Decision Points
(Ideal Data Points)
E8 68 0,1,2,3
6 Error Vector E5 65 0,1,2,3
7 Rotation Angle A7 Not Used 2,3
8 Frequency Correction A5 Not Used 2,3
9 Eye Quality Monitor (EQM) AC Not Used 2,3
Receiver Interface Memory Chip 1 (CS1)
Bit
Register
76543210
F ————————
E RIA — — — RSB RIE — RDA
D ————————
C ————————
B ————————
A ————————
9 — FED — — — CDET — —
8 — — — — P2DET — — —
7 RTH DDIS — — RCF RDIS —
6 TOD RECEIVER CONFIGURATION
5 ————————
4 ————————
3 AGC GAIN WORD (MSB)
2 AGC GAIN WORD (LSB)
1 ————————
0 RECEIVER DATA
Register
Bit
76543210
NOTE: (—) indicates reserved for modem use only.
Transmitter Interface Memory Chip 0 (CS0)
Bit
Register
76543210
F ————————
E TIA — — — TSB TIE — TBA
D ————————
C ————————
B ————————
A ————————
9 FSKT ASCR — — TCF DDEE — —
8 ————————
7 RTS TTDIS SDIS MHLD EPT TPDM XCEN SEPT
6 TRANSMITTER CONFIGURATION
5 — — CEQ LAEN LDEN A3L D3L
4 L3ACT L4ACT L4HG TLVL L2ACT LCEN
3 FREQM
2 FREQL
1 ————————
0 TRANSMITTER DATA
Register
Bit
76543210
NOTE: (—) indicates reserved for modem use only.
Receiver Interface Memory Chip 2 (CS2)
Bit
Register
76543210
F ————————
E RBIA — — — — RBIE — RBDA
D ————————
C ————————
B ————————
A ————————
9 ————————
8 ————————
7 ————————
6 ————————
5 RAM ACCESS X
4 RAM ACCESS Y
3 RAM DATA XM
2 RAM DATA XL
1 RAM DATA YM
0 RAM DATA YL
Register
Bit
76543210
NOTE: (—) indicates reserved for modem use only.
REVISIONS
L30
PRINTS TO