Specifications

19A705178
REV NO. TITLE
CONT ON SHEET
16
SH NO.
15
ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
R Sager
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
CONT ON SHEET
16
SH NO.
15
REVISIONS
L30
PRINTS TO
R96FT Hardware Circuits
Name Type Pin No. Description
A. OVERHEAD:
Ground (A)
Ground (D)
+5 volts
+12 volts
-12 volts
POR
AGND
DGND
PWR
PWR
PWR
I/OB
31C, 32C
3C, 8C, 5A, 10A
19C, 23C, 26C, 30C
15A
12A
13C
Analog Ground Return
Digital Ground Return
+5 Vdc Supply
+12 Vdc Supply
-12 Vdc Supply
Power-on-reset
B. MICROPROCESSOR INTERFACE:
D7
D6
D5
D4
D3
D2
D1
D0
RS3
RS2
RS1
RS0
CS0
CS1
CS2
READ
WRITE
IRQ
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
I/OA
IA
IA
IA
IA
IA
IA
IA
IA
IA
OB
1C
1A
2C
CA
3A
4C
4A
5C
6C
6A
7C
7A
10C
9C
9A
12C
11A
11C
Data Bus (8 Bits)
Register Select (4 Bits)
Chip Select -
Transmitter Device
Chip Select - Receiver
Sample Rate Device
Chip Select - Receiver
Baud Rate Device
Read Enable
Write Enable
Interrupt Request
C. V.24 INTERFACE:
RDCLK
TDCLK
XTCLK
RTS
CTS
TXD
RXD
RLSD
OC
OC
IB
IB
OC
IB
OC
OC
21A
23A
22A
25A
25C
24C
22C
24A
Receive Data Clock
Transmit Data Clock
External Transmit Clock
Request to Send
Clear to Send
Transmitter Data
Receiver Data
Received Line Signal
Detector
D. ANCILLARY CIRCUITS:
RBCLK
TBCLK
FRXD
FRLSD
OC
OC
OD
OD
26A
27C
16A
17C
Receiver Baud Clock
Transmitter Baud Clock
FSK Receiver Data
(inverted data)
FSK Received Line
Signal Detector
E. ANALOG SIGNALS:
TXA
RXA
AUXIN
AA
AB
AC
31A
32A
30A
Transmitter Analog Output
Receiver Analog Input
Auxiliary Analog Input
F. DIAGNOSTIC:
EYEX
EYEY
EYECLK
EYESYNC
OC
OC
OA
OA
15C
14A
14C
13A
Eye Pattern Data - X Axis
Eye Pattern Data - Y Axis
Eye Pattern Data
Eye Pattern Synchronizing
Signal
Eye Pattern Generation
The four hardware diagnostic circuits, identified in the
following table, allow the user to generate and display an
eye pattern. Circuits EYEX and EYEY serially present eye
pattern data for the horizontal and vertical display inputs
respectively. The 8 bit data words are shifted out most
Significant bit first, clocked by the rising edge of the
EYECLK output. The EYESYNC output is provided for
word synchronization. The falling edge of EYESYNC may
be used to transfer the 8-bit word from the shift register to
a holding register. Digital to analog conversion can then be
performed for driving the X and Y inputs of an
oscilloscope.
Microprocessor Timing
Microprocessor Interface Timing Diagram
Critical Timing Requirements
Characteristic Symbol Min Max. Units
CSi, RSi setup time prior
to Read or Write TCS 30 — nsec
Data access time after Read TDA — 140 nsec
Data hold time after Read TDH 10 50 nsec
CSi, RSi hold time after
Read or Write TCH 10 — nsec
Write data setup time TWDS 75 — nsec
Write data hold time TWDH 10 — nsec
Write strobe pulse width TWR 75 — nsec