Specifications

19A705178
REV NO. TITLE
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ROCKWELL MODEM TEST
SPECIFICATION/PURCHASE PART DRAWING
CONT ON SHEET SH NO. FIRST MADE FOR
F. C. F. O.
MADE BY
R Sager
APPROVALS
DCB
M. R. P. D.
DIV OR DEPT.
19A705178
ISSUED
Nov. 19, 1986
11-18-86
LYNCHBURG
LOCATION
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REVISIONS
L30
PRINTS TO
Scrambler/Descrambler
The R96FT incorporates a self-synchronizing scrambler/
descrambler. This facility is in accordance with either V.27
bis/ter or V.29 depending on the selected configuration.
The scrambler/descrambler facilities for Gearshift can be
selected to be in accordance with either V.27 bis/ter or
V.29. The scrambler/descrambler selection is made by
writing the appropriate configuration codes into the
transmitter and receiver.
Received Signal Frequency Tolerance
The receiver circuit of the R96FT can adapt to received
frequency error of up to ±10 Hz with less than 0.2 dB
degradation in BER performance.
During fast train polling, frequency offset must be less than
±2 Hz for successful training.
Receive Level
The receiver circuit of the modem satisfies all specific
performance requirements for received line signal levels
from 0 dBm to -43 dBm. The received line signal level is
measured at the receiver analog input (RXA).
Receive Timing
The R96FT provides a data derived Receive Data Clock
(RDCLK) output in the form of a squarewave. The low-to-
high transitions of this output coincide with the centers of
received data bits. For the Gearshift configuration, the first
32 bauds of data are at 2400 bps followed by 4800 bps data
for the remaining message. The timing recovery circuit is
capable of racking a ±0.0l% frequency error in the transmit
timing source. RDCLK duty cycle is 50.% ±1%.
Transmit Level
The transmitter output level is accurate to ±1.0 dB and is
programmable from -l.0 dBm to -l5.0 dBm in 2dB steps.
Transmit Timing
The R96FT provides a Transmit Data Clock (TDCLK)
output with the following characteristics:
1. Frequency. Selected data rate of 9600,7200.4800,2400
or 300 Hz (±0.01%). For the Gearshift configuration,
TDCLK is a 2400 Hz clock for the first 32 bauds of
data and a 4800 Hz clock for the remaining message.
2. Duty Cycle. 50% ±1%
Input data presented on TXD is sampled by the R96FT at
the low-to-high transition of TDCLK. Data on TXD must
be stable for at least one microsecond prior to the rising
edge of TDCLK and remain stable for at least one
microsecond after the rising edge of TDCLK.
External Transmit Clock
The transmitter Data clock (TDCLK) can be phase locked
to a signal on input XTCLK. This input signal must equal
the desired data rate ±0.01 with a duty cycle of 50% ±20%.
Train On Data
When train on data is enabled (by setting a bit in the
interface memory), the modem monitors the EOM signal. If
EOM indicates a loss of equalization (i.e., BER
approximately 10
-3
for 0.5 seconds) the modem attempts to
retrain on the data stream. The time for retrain is typically
3 to 15 seconds.
Turn-On Sequence
A total of 20 selectable turn-on sequences can be generated
as defined in the following table: