Specifications

counter, a phase/frequency comparator and a frequency lock detector. The operation of this integrated circuit is
controlled by the radio’s microprocessor through a serial data line.
Reference Oscillator
Crystal X2, varactor D122, a thermistor/resistor network and the oscillator stage of IC118 form a temperature
compensated 12.8 MHz oscillator. This frequency is divided by 2048 to generate the 6.25 kHz frequency for the PLL
frequency synthesizer. This reference determines the frequency stability of the overall radio.
Voltage Controlled Oscillator
Transistor Q115 and its associated circuitry form a voltage controlled oscillator which is voltage tuned and band
switched by varactor diodes D123 and D110. the VCO output is buffered and isolated by Q117, Q118 and Q119.
Audio modulation is applied to the cathodes of D123 and D110 to produce frequency modulation during transmit.
Dual Modulus Prescaler
The internal dividers within IC118 are not able to operate at the VCO output frequency. To alleviate this problem,
part of the overall frequency division necessary between the VCO and the phase/frequency comparator is placed
external to, and controlled by, IC118. IC117 divides the VCO frequency by 128 or 129, determined by the state of
IC118 pin 6. This produces a lower frequency which can be further divided by IC108. By strategic timing when to
divide by 128 or 129, the overall division will be that necessary to put the VCO on the correct frequency.
Loop Filter
Resistors R317 through R322 and capacitors C291, C294 and C295 form the loop filter. The purpose of the loop
filter is to filter out the 6.25 kHz reference frequency products from the output of phase/frequency comparator IC118
and to determine the dynamic operation of the overall loop.
R316, C289, Q113 and Q114 act to speed up operation of the synthesizer loop during channel changes and during
frequency transition (receive to transmit and transmit to receive).
Out-of-Lock Detector
IC118 contains a circuit which compares the timing difference of the 6.25 kHz reference frequency and the divided
down VCO frequency. The output is a 6.25 kHz pulse whose duration is equal to the timing difference. R306 and
C274 filter this pulse and average it producing a DC voltage which is proportional to the pulse width. When the loop
is in lock, this voltage is zero, but when the loop is out of lock, it rises to a level which will forward bias Q112. The
output of Q112 drives the microprocessor. The microprocessor will not allow the radio to transmit unless the
synthesizer is in lock. This is to prevent out of band signals from being transmitted.
MONOGRAM SERIES LBI-38865
CIRCUIT ANALYSIS
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Nov. 94