Specifications

Reference Oscillator
Crystal X3, varactor diode D119, a thermistor/resistor network and oscillator stage of IC108 from a temperature
compensated 10.24 MHz oscillator. This frequency is divided by 2084 to generate the 5 kHz reference frequency for
the PLL frequency synthesizer. This reference determines the frequency stability of the overall radio.
Voltage Controlled Oscillator
FET transistor Q112 and its associated circuitry form a grounded gate oscillator which is voltage tuned by varactor
diodes D120 and D121 and which is bandswitched by diodes D122 and D123 (D126 and D127 for Low band). The
VCO output is buffered and isolated by Q113, Q114 and Q119. Audio modulation is applied to the source of Q112
to produce frequency modulation during transmit.
Dual Modulus Prescaler
The internal dividers within IC108 are not able to operate at the VCO output frequency. To alleviate this problem,
part of the overall frequency division necessary between the VCO and the phase/frequency comparator is placed
external to, and controlled by, IC108. IC109 divides the VCO frequency by 64 or 65, determined by the state of
IC108 pin 6. This produces a lower frequency which can be further divided by IC108. By strategic timing when to
divide by 64 or 65, the overall division will be that necessary to put the VCO on the correct frequency.
Loop Filter
Resistors R316, R323, R324, R325, R326 and capacitors C263, C264 and C265 form the loop filter. The purpose of
the loop filter is to filter out the 5 kHz reference frequency products from the output of phase/frequency comparator
IC108 and to determine the dynamic operation of the overall loop.
R315, C262, Q107 and Q108 act to speed up operation of the synthesizer loop during channel changes and during
frequency transition (receive to transmit and transmit to receive).
Out-Of-Lock Detector
IC108 contains a circuit which compares the timing difference of the 5 kHz reference frequency and the divided
down VCO frequency. The output is a 5 kHz pulse whose duration is equal to the timing difference. R312 and C295
filter this pulse and average it producing a DC voltage which is proportional to the pulse width. When the loop is in
lock, this voltage is zero, but when the loop is in lock, this voltage is zero, but when the loop is out of lock, it rises to
a level which will forward bias Q106. The output of Q106 drives the microprocessor. The microprocessor will not
allow the radio to transmit unless the synthesizer is in lock. This is to prevent out of band signals from being
transmitted.
MONOGRAM SERIES LBI-38864B
CIRCUIT ANALYSIS
Page -13-
Nov. 94