Reference Manual

Transmission Interface Handling G.703 2048 kbit/s
Table 147 Timeslot 0 and CRC-4 multiframe structure
Bit 1 to 8 of timeslot 0
Sub
multi
frame
Frame
number
1 2 3 4 5 6 7 8
0
c1 0 0 1 1 0 1 1
1 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
2 c2 0 0 1 1 0 1 1
3 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
1 4 c3 0 0 1 1 0 1 1
5 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
6 c4 0 0 1 1 0 1 1
7 0 1 A Sa4 Sa5 Sa6 Sa7 Sa8
8 cl 0 0 1 1 0 1 1
9 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
10 c2 0 0 1 1 0 1 1
2 11 1 1 A Sa4 Sa5 Sa6 Sa7 Sa8
12 c3 0 0 1 1 0 1 1
13 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8
14 c4 0 0 1 1 0 1 1
15 E 1 A Sa4 Sa5 Sa6 Sa7 Sa8
CRC-4 Cyclic Redundancy Check (ITU-T G.704)
c1, c2, c3, c4 CRC-4 bits (see the section Layer 1
Termination 2048 kbit/s below)
A Alarm bit (see the section Layer 1
Termination 2048 kbit/s below)
E Error bit (see the section Layer 1
Termination 2048 kbit/s below)
Sa4, Sa5, Sa6, Sa7, Sa8 Spare bits (see the section Layer 1
Termination 2048 kbit/s below)
Downstream The path for information from the BSC to
the MS, see Figure 104 on page 351
Upstream The path for information from the MS to
the BSC, see Figure 104 on page 351
Linear Cascade Chain A cascade of RBS:s according to Figure
104 on page 351
350 (421)
EN/LZT 720 0008 R1A
2001-06-26
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