Specifications

Rev. 1.1 EPSON 3–29
S1D12205 Series
S1D12205
Series
(2) MPU bus write timing (68 series)
*1 The input signal rise and fall times (
tr, tf) are defined to be 25 nsec max (except for RES input).
*2 “
tEWH” is defined by the overlap time of CS LOW level and E HIGH level.
t CYC6
t AW6
t EWL
t AC6
t EWH
t AH6
t DS6
t DH6
E
CS
A0
D0 to D7
V SS x 0.8 [V]
V
SS x 0.2 [V]
t r t f
(Ta = –30 to +85°C, VSS = –3.6V to –1.7V)
Item Signal Symbol Conditions Min. Max. Unit
Address setup time
A0
tAW6 60 –
Address hold time
tAH6 50 – ns
CS setup time
CS
tAC6 0–
System cycle time tCYC6
All timing must be based on
1850 – ns
Enable LOW pulse width (Write) WR tEWL
20% and 80% of VSS.
1650 – ns
Enable HIGH pulse width (Write) tEWH 150 – ns
Data setup time
D0 to D7
tDS6 20 –
Data hold time
tDH6 80 –
ns
(Ta = –30 to +85°C, VSS = –3.3V to –2.7V)
Item Signal Symbol Conditions Min. Max. Unit
Address setup time
A0
tAW6 60 –
Address hold time
tAH6 30 – ns
CS setup time
CS
tAC6 0–
System cycle time tCYC6
All timing must be based on
1150 – ns
Enable LOW pulse width (Write) WR tEWL
20% and 80% of VSS.
1000 – ns
Enable HIGH pulse width (Write) tEWH 100 – ns
Data setup time
D0 to D7
tDS6 20 –
Data hold time
tDH6 50 –
ns