Specifications

3–28 EPSON Rev. 1.1
S1D12205 Series
11. TIMING CHARACTERISTICS
(1) MPU bus write timing (80 series)
*1 The input signal rise and fall times (
tr, tf) are defined to be 25 nsec max (except for RES input).
*2 “
tCCL” is defined by the overlap time of CS LOW level and WR LOW level.
A0
WR
D0 to D7
t
AH8
t CYC8
t AC8
t AW8
t CCL
t CCH
t DS8
t DH8
CS
VSS x 0.8 [V]
V
SS x 0.2 [V]
tr tf
(Ta = –30 to +85°C, VSS = –3.3V to –2.7V)
Item Signal Symbol Conditions Min. Max. Unit
Address setup time
A0
tAW8 60 —
Address hold time
tAH8 30 — ns
CS setup time
CS
tAC8 0—
System cycle time tCYC8
All timing must be based on
1150 — ns
Write LOW pulse width (Write) WR tCCL
20% and 80% of VSS.
100 — ns
Write HIGH pulse width (Write) tCCH 1000 — ns
Data setup time
D0 to D7
tDS8 20 —
Data hold time
tDH8 20 —
ns
(Ta = –30 to +85°C, VSS = –3.6V to –1.7V)
Item Signal Symbol Conditions Min. Max. Unit
Address setup time
A0
tAW8 60 —
Address hold time
tAH8 30 — ns
CS setup time
CS
tAC8 0—
System cycle time tCYC8
All timing must be based on
1850 — ns
Write LOW pulse width (Write) WR tCCL
20% and 80% of VSS.
150 — ns
Write HIGH pulse width (Write) tCCH 1650 — ns
Data setup time
D0 to D7
tDS8 50 —
Data hold time
tDH8 50 —
ns