Specifications

Rev. 1.1 EPSON 3–27
S1D12205 Series
S1D12205
Series
*1 Although the wide operating character range is guaranteed, a quick and excessive voltage variation may not be
guaranteed during access by the MPU. The low-voltage data hold characteristics are valid during Sleep mode. No
access by the MPU is allowed during this time.
*2 D0 to D5, D6 (SCL), D7 (SI), A0, RES, CS, WR (E), PS, IF, C86
*3 The resistance if a 0.1-volt voltage is supplied between the SEGn, SEGSn, COMn or COMSn output pin and each
power pin (V
1, V2, V3 or V4). It is defined within power voltage (2).
R
ON = 0.1V/∆I
where, ∆I is current that flows when the 0.1-volt voltage is supplied between the power supply and output.
*4 Applied if not accessed by the MPU during character display and if the built-in power circuit and oscillator are
operating.
Display character:
*5 Current consumption if always written in “fcyc”. The current consumption during access is roughly proportional to
the access frequency (fcyc).
*6 The “
tR” (reset time) indicates a time period from the rising edge of RES signal to the completion of internal circuit
reset. Therefore, the S1D12205 Series enters the normal operation status after “
tR”.
*7 Defines the minimum pulse width of RES signal. A pulse width greater than “
tRW” must be entered for reset.
V DD
V SS
V DD
V SS
–2.4 V
t RES
t RW t R
RES
All signal timings are based on 20% and 80% of Vss.
*8 The following provides the relationship between the oscillator frequency (fOSC) for built-in circuit driving and the
frame frequency (f
FR).
f
OSC = 13 × 26 × fFR (3-line display)
= 13 × 18 × f
FR (2-line display)
<Reference>
f
BLK = (1/128) × fFR
*9 Enter the waveforms in 40% to 60% duty to use an external clock instead of the built-in oscillator. If no external clock
is entered, fix it to HIGH. (Normal HIGH)