Specifications
3–10 EPSON Rev. 1.1
S1D12205 Series
Figure 1
Data bus signal identification
The S1D12205 Series identifies the data bus based on a
combination of A0, WR and E signals as defined on
Table 3.
Table 3
Chip Select
The S1D12205 Series has an Chip Select pin (CS) to
allow an MPU interface input only if CS=LOW.
During no chip select status, all of D0 to D7, A0, WR, SI
and SCL inputs are made invalid. If the serial input
interface is selected, the shift register and counter are
reset.
However, the Reset signal is entered independent from
the CS status.
Power Circuit
The built-in power circuit featuring the low power
consumption generates the required LCD drive voltages.
The power circuit consists of an booster and a voltage
regulator.
Booster Circuit
When the capacitors are connected to the OCA, OCB,
OCC, OCD, OCE, V
REG2 pins, the LCD drive voltages
are generated.
As the booster uses the signals from the oscillator, the
oscillator or an external clock must be operating.
The following provides the potential relationship.
SCL 1
A0
SI
CS
D7 D6 D5 D4 D3 D2 D1 D0 D7
2345678
A0
1
Common 68 Series 80 Series
Function
A0 E WR
1 1 0 Writes to the RAM and symbol register.
0 1 0 Writes to the internal (commands) register.
LCD drive voltages
V
0
= V
DD
V
1
V
2
, V
3
V
4
V
5
V
REG2
V
5
= 4 x V
REG2
Voltage
drop
Voltage boost
V
DD
= 0V
V
SS