Specifications

Rev. 1.1 EPSON 3–7
S1D12205 Series
S1D12205
Series
System Bus Connector Pins
Pin Name I/O Descrition No. of Pins
An 8-bit input data bus to be connected to the standard 8- or 16-bit MPU data bus.
Pins D7 and D6 function as the serial data and clock inputs respectively if PS is
logical low.
D7(SI)
D6(SCL) I 8
D5 to D0
Open : May be open. However, the potential is recommended to fix to have
better noise-resistance characteristics.
- : May be HIGH or LOW. However, the potential must be fixed.
Usually, the most significant bit of MPU address bus is connected to identify data
A0 I
or command.
1
0: Indicates D0 to D7 are command.
1: Indicates D0 to D7 are display data.
RES I Initializes when RES is set to LOW. The system is reset at RES signal level. 1
CS I
A Chip Select signal. The address bus signal is decoded and entered.
1
This is valid when LOW.
- When an 80-series MPU is connected
Active LOW.
The WR signal of 80-series MPU is connected. The data bus signal is fetched
WR
I
at the rising edge of WR signal.
1
- When a 68-series MPU is connected
Active HIGH.
Used as an Enable Clock input of 68-series MPU. The data bus signal is
fetched at the falling edge of WR signal.
A switching pin between serial data input and parallel data input.
PS I 1
An interface data length select pin during parallel data input.
IF I
- 8-bit parallel input if IF=HIGH
1
- 4-bit parallel input if IF=LOW
This pin is connected to VDD or VSS if PS=LOW.
An MPU interface switch pin.
C86 I
- 68-series MPU interface if C86=HIGH
1
- 80-series MPU interface if C86=LOW
This pin is connected to VDD or VSS if PS=LOW.
An external clock input pin.
CK I
It must be fixed to HIGH to use the internal oscillator.
1
To use an external clock input, turn the internal oscillator OFF by issuing the
command.
P/S Chip select Data/Command Data Serial Clock
HIGH CS A0 D0 to D7 —
LOW CS A0 SI SCL
PS C86 IF D7 D6 D5 D4 D3 to D0 CS A0 WR
LOW — — SI SCL OPEN OPEN OPEN CS A0 —
HIGH HIGH HIGH D7 D6 D5 D4 D3-D0 CS A0 E
HIGH HIGH LOW D7 D6 D5 D4 OPEN CS A0 E
HIGH LOW HIGH D7 D6 D5 D4 D3-D0 CS A0 WR
HIGH LOW LOW D7 D6 D5 D4 OPEN CS A0 WR